OSU RISC-V Caravel

This is an implementation of a single-cycle RISC-V processor inside of the Caravel test system for use in the SkyWater 130nm PDK.

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Owner

James Stine

Organization URL

https://vlsiarch.ecen.okstate.edu/

Summary

Caravel_RISCV_OSU is an implementation of a single-cycle RISC-V processor inside of the Caravel test harness intended for use with the SkyWater 130nm PDK.