Logo

Caravel_RISCV_OSU

public

OSU RISC-V Caravel

This is an implementation of a single-cycle RISC-V processor inside of the Caravel test system for use in the SkyWater 130nm PDK.

If you are collaborating on this project, please click here to access your collaboration files, and click "Accept Share" in the actions column if you haven't done so already.

project layout image
project layout image
Layout Image
Owner

James Stine

Summary

Caravel_RISCV_OSU is an implementation of a single-cycle RISC-V processor inside of the Caravel test harness intended for use with the SkyWater 130nm PDK.

Version

0.1

Category

Test Harness

Process

SKY130

Shuttle Tags

Open MPW

MPW-1

Last MPW Precheck

Failed

12/16/20 14:44:12 PST