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Sub-Sampling PLL...
public project

Implementation of a Sub-Sampling PLL targeting SerDes Applications

Motivation:

Frequency references are a key part of all kinds of digital circuits, wireless applications, and communication systems in general. Crystal references are very stable and reliable, but only output frequencies in the range of tens of MHz. For any application relying on frequencies above that, an indirect frequency generation using a PLL becomes vital.

The challenges coming along while designing a PLL are noise/jitter as well as power consumption. The generated output frequency should be as stable as possible and immune to noise interferences. With the wide-ranging applications of the PLL and the challenges combined, it is a neat topic to keep working on to find optimizations and improvements.

Project description:

The aim of this project is to design a hybrid form of the PLL for a frequency range of about
1 GHz – 2 GHz using the SKYWATER PDK 130nm process. The supply voltage will be 1.8V.

The focus lies on the theory, analysis, design and layout of the complete circuit. 

The overall design of the PLL will include four main blocks which are designed and optimized individually: sub-sampling phase detector, VCO (voltage-controlled oscillator), integer-N frequency divider, and frequency locker loop.

The sub-sampling phase detector compares the external reference input and the output of the frequency divider, hence the output of the VCO. Deviations are being counteracted by two separate paths: a coarse-tuning and a fine-tuning path which both control the VCO. The coarse-tuning path will include a DAC and a control unit. The fine-tuning path will include the sub-sampling phase detector with a gmC-filter. The implementation of a sub-sampling architecture leads to better noise performance.

The frequency locker loop will include another frequency divider as well as the control unit for the DAC. The digital part will be responsible for implementing the coarse-tuning path of the design. The control unit of the DAC will set its value according to the frequency mismatch between the reference frequency and the output frequency of the divider, hence, the VCO.

The VCO will be implemented as a ring structure using pseudo-differential delay cells. Although ring VCOs have inherently higher phase noise than corresponding LC oscillators, they have two main advantages: small integration area and wide tuning range compared to LC-VCOs. The used delay cells provide a large signal range and therefore good noise performance, good CMRR and an unrestricted number of delay cells. An additional advantage is the availability of multiple phase-shifted signals after each delay stage which are available for further processing.

Since the VCO and the analog paths are sensitive to supply noise, an LDO regulator (Low Drop Out) will be implemented to supply these two blocks. An advantage of a hybrid implementation is the lower power consumption since the digital parts can be switched off if not needed.

Proposed Architecture:

The proposed PLL architecture includes the sub-sampling phase detector, the ring VCO, the frequency locked loop and some buffers and frequency dividers. This specific architecture leads to better performance, faster locking time, and better noise rejection.

The overall block schematic shows the main parts of the proposed sub-sampling PLL.

The proposed architecture for the pseudo-differential delay cell consists of a differential pair, cross-coupled load, and two MOSFETs in diode-connection. Two transistors are used to change the gain of the delay cell and therefore the delay time based on the value of the control voltage.

The structure of the ring VCO will look like the proposal above. There is a phase shift after each stage (VA, VB, VC), which could theoretically be used in other applications if the whole PLL circuit is embedded in a greater design. The number of stages is determined by the desired frequency of the application. Also, some of the stages will be controlled by the coarse-tuning path and some by the fine-tuning path, providing fast and stable frequency locking.

Frequency division is done in the feedback path of the PLL. Proposed is a division by 2 at the output of the ring VCO. All dividers in the architecture will be integer-N dividers.

The sub-sampling circuit will feature a gmC-Filter with an overlap control. The reference frequency is provided by the reference clock (including a buffer). The input from the VCO is already divided by 2. The output voltage is the fine-tuning path of the VCO. 

Goals:

The goal is to realize a hybrid form of the PLL so that the advantages of both “worlds” can be harvested. This ensures smooth functionality, low jitter and noise, and, therefore, very stable output frequency. Therefore, the focus of the design lies within a low noise figure and low jitter as well as low power consumption. The layout will be done using the SKYWATER PDK 130nm process, simulations are carried out with XSchem/ngspice and Xyce.

Target performance table:

Technology                             Skywater 130 nm

Supply voltage                        1.8V

Output Frequency                  1.0 – 2.0 GHz

Reference Frequency            10 – 100 MHz

Tools:

All tools used throughout this proposal are open-source, easily obtainable, and feature proper maintenance and online support.

The schematic of the proposed architecture will be designed using XSchem.

Simulations will be carried out using ngspice and Xyce.

The final layout will be done using magic with the SKYWATER PDK 130nm process.

Team:

Christof Gindu, BSc

Rohish Kumar Reddy Mitta, MSc

Univ.-Prof. Dr. Harald Pretl

References:

[1] A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7nm FinFET CMOS

Featuring 0.619ps Integrated Jitter and 0.6us Settling Time at 2.3mW

Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski

TSMC, Hsinchu, Taiwan, University College Dublin, Dublin, Ireland

 

[2] A Low-Jitter and Low-Spur Charge-Sampling PLL

Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie

 

[3] A Low-Jitter Sub-Sampling PLL with a Sub-Sampling DLL

Yuan Cheng Qian, Yen Yu Chao, and Shen Iuan Liu

 

[4] Wideband PLL System as a Clock Divider

Aylin Donmez, Delft University of Technology

 

[5] Frequency Divider Design for Multi-GHz PLL Systems

Francesco Barale, Georgia Institute of Technology

 

[6] A 0.008mm2 2.4GHz Type-I Sub-Sampling Ring-Oscillator-based Phase-Locked Loop with a
-239.7dB FoM and -64dBc Reference Spurs

Shravan S. Nagam, Peter R. Kinget
Dept. of Electrical Engineering, Columbia University, New York

 

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Owner

Christof Gindu

Summary

The goal is to realize a hybrid form of the PLL so that the advantages of both “worlds” can be harvested. This ensures smooth functionality, low jitter and noise, and, therefore, very stable output frequency. Therefore, the focus of the design lies within a low noise figure and low jitter as well as low power consumption. The layout will be done using the SKYWATER PDK 130nm process, simulations are carried out with XSchem/ngspice and Xyce.

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