SSCS PICO CHIP 3 is a collaboration between teams Austria, Brazil, and USA1. The three designs includes on the chip are a Sub-Sampling PLL, a 60 GHz demonstrator chip and a Low Power 10b SAR-ADC. 

Austria: Sub-Sampling PLL

https://platform.efabless.com/projects/923

The goal is to realize a hybrid form of the PLL so that the advantages of both “worlds” can be harvested. This ensures smooth functionality, low jitter and noise, and, therefore, very stable output frequency. Therefore, the focus of the design lies within a low noise figure and low jitter as well as low power consumption. The layout will be done using the SKYWATER PDK 130nm process, simulations are carried out with XSchem/ngspice and Xyce.

Brazil: 60 Ghz Demonstrator

https://platform.efabless.com/projects/920

The goal is to build a demonstrator chip in the 10 mm² user project area to assess the feasibility of implementing mm-wave designs in a low-cost technology using a complete open-source RFIC design flow. We propose to submit a number of basic mm-wave circuits, such as voltage-controlled oscillator, power amplifier, balun, low-noise amplifier and detector, as well as some test features like inductors, (slow-wave) transmission lines and a basic TRL calibration kit.

USA1: Low Power 10b SAR ADC

https://platform.efabless.com/projects/851

This project aims to create a 10 bit SAR ADC with the goals of extending useful mixed-signal IP for the sky130 node and educating emerging IC designers. This will be a collaborative effort between MIT Lincoln Labs IC designers and UAH faculty/undergraduate students. The results will open SAR ADC designs as well as material for an upcoming undergraduate/graduate course in open-source IC design to be offered at UAH in Spring 2023.