Efabless Logo

Tag Search

"profiles" search for "interests": uvm
Open Search

Number of Results: 4

entry image

R.Thanga Gnana Jenef

Actively Looking to work in a Semiconductor Organisation.I'm undergoing Masters in VLSI. I am Passionate about VLSI and semiconductors.He recently completed the 6-months training in Back-end VLSI at Entuple Technologies. And in addition to that specifically trained in STA, Synthesis and Physical Design by employing Cadence Tools. He is interested in and currently working on Open-Source tools related to VLSI (Openlane)

Skills

cadence Openlane Tanner Mentor Graphics

Area of Expertise

Academic: Student
entry image

vinay k s

Verification engineer and quick learner and really enthusiastic to learn new things

Skills

Perl System Verilog Verilog

Area of Expertise

SoC: Verification
entry image

Manish Mahajan

I am a design / verification Engineer for ASIC and FPGA .

Skills

C/C++ System Verilog Tcl/Tk Verilog

Area of Expertise

Digital: RTL Digital: Verification
entry image

Paulo Roberto Bueno de Carvalho

Skills

C/C++ Cadence Encounter System Verilog Verilog

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification