Analog IC Design Engineer with considerable expertise in mid- to high-frequency transistor-level design in the semiconductor industry, including clock synthesis, radio frequency circuitry (RF), and memory circuitry design. Experience also includes testing at board- and wafer-level, test automation, and simulation scripting.
I am a software developer, trying to learn about hardware design
I'm an AMS Design engineer. I like the IC design world and my recent goal is to be a scientist :)
VLSI circuit design engineer with significant experience in microprocessor design in semiconductor processes from 65nm to 10nm. Provided register file designs and design training for Intel Big Core and SOC projects. Helped create semi-automated array layout methodology. Established cross-organizational methodology for variation analysis in register files. Converged memory IP handling across multiple organizations.
Manager of Universal Avionics System Corporation(UASC) PLD design group. This group is tasked with designing, implementing and approving, in accordance with RTCA/DO-254 guidance, all ASIC/FPGA used in the Universal Avionics product line.
I am a digital design/verification engineer. I have 2 years of full-time industry experience. In total, I have 4.5 years of experience in RTL design, Electronic Design Automation and Verification using VHDL/Verilog, Perl, Tcl and Linux. I was the #1 graduate of Bahcesehir University in Mechatronics Engineering in 2013
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.
Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)
Physical design engineer
Experienced Analog Design Engineer with strong background in HV CMOS ASICs.
Vice President of Engineering - Seamless Microsystems. We design high performance AFEs using proprietary and patented technology that encodes the signal in the time-domain instead of voltage or current. This enables us to design low-power ADCs and amplifiers in scaled CMOS. Contact us if you'd like to hear more and engage our services.
Expert in embedded and mobile applications since 2003. Has many years of experience in software and hardware development, effective team management. Excellent in the research and development, technology findings and implementations.
Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.
A recent graduate student from Syracuse University major in Electrical Engineering with focus in VLSI Designs
Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.
I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.
ASIC architect and designer. Specialize in deep learning, video, image and signal processing, and compression. Professor of Electrical and Computer Engineering at The College of New Jersey.
Edward Joullian Endowed Chair in Engineering Oklahoma State University Department of Electrical and Computer Engineering VLSI Computer Architecture Research Group
Assistant Professor (IISc) | Ph.D. & S.M. (MIT) | B.Tech. (IIT-KGP)
Principal engineer leading PNT product development at GE Aerospace
Doctoral student at the Tokyo Institute of Technology.
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
PhD student working on a superconducting FPGA design aiming to work on neuromorphic computing in the future.
Current iOS Programmer, EE with decade of physical design experience in mixed signal - worked on POWER architecture PLLS.
I am professor at Dept of EEE, BUET, Passionate to teach students IC Design and Fabrication Skill.
Experienced Senior Design Engineer with a demonstrated history of working in the electrical and electronic manufacturing industry. Skilled in DAC, SPICE, ADCs, Electronics Hardware Design, and Management. Strong engineering professional with a M-Tech focused in VLSI System Designs from Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering &Technology and also a B-Tech Degree in the field of Electrical, Electronics and Communications Engineering from Mahatma Gandhi Institute of Technology.
Cryptography and security researcher at Seagate Technology
13+yr ASIC Digital Designer. Master degree on Microeletronic Sensors. Worked on NXP through different projects on automotive and consumer/general market MCUs on areas from SoC Integration to Timing Sign-Off
Semiconductor professional with 12+ year experience in ASIC hardware design and methodology development. Main expertise is in chip STA signoff - top level, IO timing, High speed design timing, and good knowledge of RTL design, Physical design (Layout, CTS, Route, DRCs), Synthesis and Formal Verification. Have also completed business management studies and looking for interesting opportunities in chip product development and management.
I am a novice, building a Test chip for the first time
IC design Engineer
Hon-Piu Lam, is a Ph.D. candidate in the Department of Electronic and Computer Engineering of the Hong Kong University of Science and Technology (HKUST). He was an analog IC designer engineer in Valence Semiconductor from 2004 to 2007. From 2007 to 2015, he joined Fujitsu Semiconductor focusing on the embedded NOR flash design. He has been a researcher in HKUST focusing on the integrated power electronic and data converter. His research interests include readout electronics, integrated power electronics and radiation hardened electronics for experimental physics.
Automation enthusiast (likes to code in Perl). At this time, Doing Master's in VLSI Design and working as an intern @intel. Great learning experience doing both simultaneously. Have experience designing in both circuit (Low power & timing) & device level (high performance designs for digital applications). Obtained honor of 3rd position in concept design competition by ISRO for designing temperature & radiation resistant Tunnel FET. Would love to work with all device technology enthusiasts as opportunities arise.
Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.
I'm a new grad Digital Design engineer working. Looking forward to contribute to open source silicon projects.
Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.
Hello, I'm an IC Designer Analog/RF with digital skills. I worked mainly on PLL for mobile tranceivers. I used to work on Cadence Design flow for 20 years.
Silicon Entrepreneur with extensive experience in Digital Physical Design, EDA and HPC Infrastructures for Electronic Design.
President and CEO
I am designed mixed signal ICs for Music, Audio, IoT and sensor applications.
Dad. Partner. Scientist. Activist. Maker. — He/His