20+ Years of Experience in Chip Design
Current working in my PhD at BarcelonaTech.
i am working as physical design engineer
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.
Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.
Graduated with a Micro-electronics Master from Bordeaux university, France, I have now 18 years of experience. Worked in France, England, Belgium and Brazil, within 5 companies. Implemented physical design flows, recruited, trained and supervised trainees to experienced engineers, I have a vast experience in setting up complete flow (2 companies were startups), as well as signing off important design within NXP and CSR, all to successful first time right silicons. Able to work in total independence as well as within a team, I consider myself as optimist, result focused, with attention to detail while keeping a good trade between time to market and risk taking.
Lecturer UiTM
Physical Design Engineer
Physical design engineer
Experienced Analog Design Engineer with strong background in HV CMOS ASICs.
A young and ambitious individual, eager to apply my knowledge of Computer Architecture and VLSI Physical Design to develop hardware that is performance, power and area efficient, while actively contributing to the development and growth of the open-source semi-conductor industry
Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.
Physical Design Engineer
An experienced mixed-signal IC design engineer / design manager with over 25 years experience. Has design and led the design of multiple mixed-signal ICs through to tapeout and silicon verification. Also experienced with the delivery of IP blocks. Worked across multiple market sectors.
Assistant Professor (IISc) | Ph.D. & S.M. (MIT) | B.Tech. (IIT-KGP)
I am Physical Designe Engineer -1 at Signoff Semiconductors
PhD Student Research on Integrated Sensor Interfacing Systems featuring signal conditioning and A/D conversion. Functional blocks developed: VGA, current-steering DAC, SAR ADC, AA Filters, SPI master/slave.
I am a Master's student who has to know for learning and do experiments as well as for writing technical blogger. My website links are given below to connect with my open-source family of the VLSI champions. https://nishitnathwani.blogspot.com/ https://geniusvlsi.blogspot.com/
Professor and Entrepreneur
Professor of CSE at UC Santa Cruz
I am a 3rd year electronics engineering student. I am interested in chip design and want to learn this field. www.linkedin.com/in/ferhat-böcek-b73452170
30+ years in IC design, completed several NOR/NAND flash projects, and running in production.
I'm a software engineer (operating systems architect), and a microelectronics engineer (IC designer)
RF/Analog IC design and SOC
Fresher interested in asic physical design and looking for job opportunities in physical design engineering
Chip Design CAD Expert
Physical Design over 10 years, Front-End Design over 4 years, have knowledge on DFT, STA, ...
I am interested in new things. I've designed chips from definition to polygons, mostly in the pursuit of new capabilities.
IC design Engineer
I am en Electronics Engineer currently Pursuing my Masters in IC design from FAST NUCES Islamabad.
Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.
Silicon Entrepreneur with extensive experience in Digital Physical Design, EDA and HPC Infrastructures for Electronic Design.
A digital design engineer, interested in memory hierarchies and high speed interfaces.
President and CEO
R&D Engineer
IC designer with more than 25 years post Ph.D. experience. Specialising in RF, RFIC, analog and mixed-signal. Wide experience in Architecture, system and circuit design. RF front-end module design for cellular with CMOS PA. Over 40 patents issued.
I am Pratika Tripathi. I am in my final year of Btech. I am very interested in physical designing of IC. I had even taken 3 courses of kunal ghosh sir on physical design, stay, and cts. I am doing my final year project in physical design.
For most of my career, I was a CAD technology innovator and CAD system architect at Intel Corporation. I signed up recently for a Udemy class called "VSD - Making the Raven Chip: How to Design a RISC-V SoC." The class pointed me to Efabless.
I've done everything from silicon design at the "bottom of the stack" to System Architecture and Design (with plenty of SW to go with it; at every level)
I'm the CEO of a fabless semiconductor start-up company and have more than 15 years experience in designing mixed-signal ASICs on various foundry processes.
Engineer / VP
I am Full Professor and Head in the Department of ECE, NEHU, Shillong. My research area is Silicon Photonics, Optical Communication, Photonic Integrated Circuits.
Hardware System Designer from ASIC chip to board to SOC platform
I have over thirty years of experience in the semiconductor industry, having worked in fab, EDA and design engineering. have built and led large, geographically distributed teams at a senior manager level. I am passionate about developing talent and skills, particularly in young people from socio-economically underprivileged backgrounds.
Berna Örs Yalçın received the Electronics & Communication Engineering degree and the MSc degree in 1995 and 1998, respectively, both from the Istanbul Technical University (ITU), Turkey. She received the Electrical Engineering degree in applied sciences from the Katholieke Universiteit Leuven, Belgium, in 2005. Currently, she is a Professor at ITU. Her main research interests include cryptography, embedded systems, and side-channel attacks.
FPGA/HW engineer
ASIC Designer with experience in Back-end & Front-end stages for ASIC design flow.
Senior lecturer at Vasyl Stefanyk Precarpatian National University
I am a ASIC Designer with a piqued interest in AI Hardware Design.
I'm a BTech Electronics and Instrumentation graduate and an electronics enthusiast who was inspired by the open-source silicon technology and it's accomplishment and aim to build a career for myself in VLSI specifically as an ASIC Physical Design Engineer.
RTL Design, GDS, VLSI
Since 2001 I have worked for a small IC Layout design firm located in Wilsonville, Oregon called Coast-to-Coast Layout Design Inc. We provide full-custom mask design services to big semiconductor partners, both digital and analog/mixed-signal. I began my career as a part-time Linux systems administrator, and was taught mask design by my mentor and boss, then over the past couple decades I moved up the ranks to my current GM position where I am responsible for most day-to-day operations and management of multiple mask design teams who are very highly valued by our customers that rely on our services to meet tough tapeout schedule and quality requirements. I'm here because I'm planning to use open-source EDA tools to help train new mask designers to help grow my company.
