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"profiles" search for "skills": synopsys

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Number of Results: 23

Chuan Le

Skills

Cadence Encounter Leadership Synopsys Physical design

Area of Expertise

Digital: Placement and Routing SoC: Floorplanning

Sang-Deok Park

I am interested in the platform-based complete SoC design/verification automation methodology and framework

Skills

C/C++ Python System Verilog Verilog Scala Wake Shell Synopsys EDA Tools Rust

Area of Expertise

Digital: RTL

Shankar Narayanan

Skills

physical design synopsys

Area of Expertise

SoC: Floorplanning

Mohamed Ali Younis

Skills

C/C++ Cadence Virtuoso Leadership Magic CAD Matlab System Verilog Tcl/Tk Verilog ASIC Synopsys Tools

Area of Expertise

Academic: Student Digital: Placement and Routing Digital: Synthesis

ejre

Skills

Cadence Virtuoso ngspice Python Synopsys Custom Designer Synopsys HSPICE

Area of Expertise

Academic: Research Academic: Student Analog: Design

Yunus Emre ERYILMAZ

Skills

C/C++ Python Tcl/Tk Verilog Synopsys DC NXT

Area of Expertise

Academic: Research Academic: Student Digital: Placement and Routing

Liban Hussein

Graduate student passionate about integrated circuit design for biomedical applications

Skills

Cadence Virtuoso Calibre Leadership System Verilog synopsys innovus

Area of Expertise

Analog: Design Analog: Layout Digital: RTL

Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.

Skills

C/C++ Cadence Encounter Cadence NC-Verilog Cadence Virtuoso Electric CAD Electric VLSI Design System Matlab Mentor/Siemens EDA ModelSim ngspice Octave Perl Python Software Developer Synopsys Avanwaves Synopsys Cosmos Synopsys Design Compiler Synopsys HSPICE Synopsys NanoSim Synopsys PrimeTime System Verilog System-C Tcl/Tk Verilog VHDL Xilinx ISE

Area of Expertise

Academic: Research Academic: Student Analog: Design Analog: Modeling Analog: Simulation Analog: Verification CAD: Scripting CAD: Tool Development Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Signal Processing design space exploration of VLSI system designs Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Neural Networks RTL code generation SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: Test Programming VLSI layout design

Jerry Yin

Skills

Cadence Virtuoso Calibre Magic CAD Verilog Cadence Innovus Synopsys Design Complier Synopsys ICC2 Synopsys Prime Time

Area of Expertise

Academic: Student VLSI Physical Design

Mehmet Sait Eroğlu

Skills

System Verilog Synopsys

Area of Expertise

Digital: RTL

Nandhini Jayapandian

Skills

Verilog Synopsys DC Synopsys ICC Synopsys ICC2 RedHawk

Area of Expertise

VLSI

Luis Esteban

Electrical Engineer interested in the design of mixed signal ASICs

Skills

Digital flow Cadence Synopsys Signal Processing

Area of Expertise

Digital design

Mohamed Hossam

My name is Mohamed, I'm from Egypt, I'm studying at the electronics and communications engineering department at Cairo University, I'm an undergraduate student and my expected graduation year is 2024. I am interested in digital design track, I have done many projects related to this field. I am very passionate to get this experience and I am sure that I will do great work with you.

Skills

Tcl/Tk Verilog STA Power aware Design PnR DFT CDC Synopsys Design Compilier

Area of Expertise

Academic: Student

Teng-Kiat Lee

Skills

Cadence Virtuoso Custom Compiler Synopsys

Area of Expertise

EDA Custom Design

karunakar reddy kesamreddy

I am a professional in the field of Chip Design, Primary working on Synthesis, Physical Design, Static Timing Analysis and Physical Verification

Skills

Cadence Virtuoso Cadence Innovus Cadence Genus Synopsys Prime Time Synopsys IC Compiler 2 Synopsys Fusion Compiler Synopsys Design Compiler Tweaker Synopsys IC Validator Seimens Calibre

Area of Expertise

Analog: Design Digital: Synthesis Physical Design Physical Verification Static Timing Analysis

Likhit Daggubati

Skills

Perl Python Tcl/Tk Verilog Synopsys DC Synopsys ICC2 Synopsys PT Synopsys StarRC-XT

Area of Expertise

Digital: Synthesis SoC: Floorplanning System: Chip Editing

Peter Colyer

Chip Physical Design CAD Expert with 4nm Experience. Excels at unusual assignments and large scripting/programming projects. Strong debug skills. Strong Python skills. Available for full time, part time, tutoring, mentoring, consulting. ** https://www.linkedin.com/in/petercolyer ** Chip Physical Design and CAD Flow Development; Prior Roles in Reliability, Test, and ASIC Development; Software Development. • Digital Physical Implementation; • CAD Flow Script Development; • Design Rule Manual Interpretation/Application; • BS Physics Siena College, Magna Cum Laude; • BS Electrical and Computer Engineering Clarkson University, with Great Distinction; • MS Electrical Engineering Syracuse University. Based in California USA; Based in USA

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Collaboration Debugging Extraction Correllation Flow Runtime Optimization Innovus Machine Learning Perl Power Performance Area Optimization PyTest Python Root Cause Analysis SKILL Software Development STA Correlation Synopsys fusion compiler Tcl/Tk Teamwork Technology Node Install Verilog

Area of Expertise

CAD: Scripting Digital: Placement and Routing Digital: Verification PPA PPA Optimization RISC-V SoC: Floorplanning SoC: Verification SRAM System: Chip Integration

Jakub Rachoń

I am experienced analog and mixed signals circuit designer. I am also licensed HAM radio operator with call sign SQ2SQN.

Skills

Magic CAD Netgen ngspice Octave Perl Python Tcl/Tk Verilog VHDL Synopsys

Area of Expertise

Analog: Design

Angel Trujillo

ASIC Designer with experience in Back-end & Front-end stages for ASIC design flow.

Skills

Cadence Tools Cadence Virtuoso Calibre Scilab Synopsys Tools System Verilog Tanner L-Edit Tcl/Tk Verilog

Area of Expertise

Analog: Layout CAD: Scripting Circuits: Microcontrollers Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning System: FPGA Programming

Joao Fernandes

Skills

Cadence Virtuoso Matlab Verilog-A Synopsys Custom Compiler Spice

Area of Expertise

Analog: Design Analog: Verification A&Ms Desing

Mohammed Fayiz Ferosh

I'm a BTech Electronics and Instrumentation graduate and an electronics enthusiast who was inspired by the open-source silicon technology and it's accomplishment and aim to build a career for myself in VLSI specifically as an ASIC Physical Design Engineer.

Skills

C/C++ Python Tcl/Tk Verilog Synopsys Tools opensource EDA Tools ASIC Physical Design

Area of Expertise

Academic: Student Business: Design Services CAD: Scripting Circuits: Microcontrollers Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Mohammed Salah

Experienced ASIC Digital Design and Physical Implementation Enthusiast

Skills

Cadence Encounter Tcl/Tk Verilog Synopsys Design compiler (DC) Synopsys Formality Synopsys ICC Synopsys ICC II Synopsys PrimeTime QuestaSim Vivado

Area of Expertise

Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis