open source EDA tooling dev; currently at ChipFlow and YosysHQ
I am a software developer, trying to learn about hardware design
I am a senior researcher in INESC-ID, Lisbon.
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
Principle Engineer at efabless corporation
Physical design engineer
An experimental physicist through sensor and instrumentation development.
Expert in embedded and mobile applications since 2003. Has many years of experience in software and hardware development, effective team management. Excellent in the research and development, technology findings and implementations.
I'm an engineer with experience in analog IC design both in private companies as well as academia. Experienced in design of delay locked loop(DLL), clock recovery, field detectors, voltage limiters, operational amplifiers, current mirrors, bandgap reference and so on.
EDA software engineer working on silicon CAD for Intel during the day. I've got DNA synthesis on the brain, and have been learning how to integrate micro/nano fluidics with active electronics to achieve a wholly automated "genetic compiler". Building a nano fab in my home workshop.
More than 14 years of experience in Electronic Design Automation roles with leading industry companies like Intel, Samsung and others. Have a strong background in EDA best practices and technologies like DRC, LVS, XRC, PERC and others. Have a mixed background in circuit. design, data science and programming with emphasis on data analysis for microchip design. Have strong background leading project deliveries to fortune 100 companies in the world. B.Sc. in Electrical Engineering from faculty of Engineering, Ain Shams University, Cairo, Egypt.
Professor of CSE at UC Santa Cruz
Principal engineer leading PNT product development at GE Aerospace
I am an Associate Professor teaching VLSI design, hardware security, and digital circuit design at Drexel University. My research interests include analysis, modeling, and design methodologies for high performance digital and mixed-signal integrated circuits, power management for SoC and microprocessor circuits, hardware security, including digital and analog obfuscation and Trojan detection, and electric and thermal modeling and characterization, signal and power integrity, and power and clock delivery for heterogeneous 2-D and 3-D circuits.
Developer of open source reliability verification system CVC(RV). https://github.com/d-m-bailey/cvc
PhD student working on a superconducting FPGA design aiming to work on neuromorphic computing in the future.
Program manager with more than 25 years experience in the semiconductor industry. Expertise in EDA tools, analogue, RF and high-voltage PDK development, sensor design, design support for electro-magnetic compatibility, ESD and functional safety.
High Performance, High Frequency Analog, Microwave, RF and Optical Chip and Package Test Software and Hardware, Multi-Chip System Integration and Reliability
abyssal witch | deranged catgirl hardware/software engineer + vtuber | that crazy SCSI girl | she/her
ASIC and FPGA design and verification Engineer with a sideline in bring devops to Hardware projects
Open-source software developer with 30 years experience in back-end verification.
Founder and CEO of Earth ICT, SPC NAICS 334413; Semiconductor and Related Device Manufacturing Incorporation Date: 08/03/2021 Corporation ID: C4773876 1-650-996-7232 art@earthictspc.com Biography: Dauntless Entrepreneurial Risk-taker; Invited expert, ITU-T ICT Sector L.TIME (The IC Metric for Energy-efficiency, Quality-Factor) Recommendation. “Art is many faceted; he creates outside the box; he is a serial entrepreneur-intrapreneur and change agent, and is flexible-adaptable-situational. He has worked for Silicon Valley icons such as SRI, Applicon, Computer Sciences Corporation, Informatics, Atari R&D, Interactive Research Corp., Samsung Information Systems America. And he has participated in several startups: Digital Video Inc. (1985–2001), Ravisent Technologies (1998–1999)” [source: ”Sustainable computing - ACM ]
I am the founder of Aurifex Labs LLC. I have a BSEE from Wilkes University. I've spent most of my time in software, education, and entrepreneurship, but have spent the past year learning VLSI and am excited for this new era of open source hardware/tools.
Experienced Senior Technology Manager with a demonstrated history of working in the semiconductor and Hi-Tech industry, High-Performance Computing (HPC) information technology, and services industry. Skilled in IT Infrastructure Management, sales enablement, semiconductor design development, and Electronic Design Automation software development. Strong business development professional from Harvard Business Analytics Program.
Dad. Partner. Scientist. Activist. Maker. — He/Him
IC design Engineer
A student of Keio Univ in Japan, interested in analog circuits rather than digital ones.
D Gracia Nirmala Rani received the B.E. degree in Electronics and Communication Engineering from Syed Ammal Engg College, Madurai, India, in 2004, and M.E. degree in VLSI Design from Karunya University, Coimbatore, India in 2007. She has awarded Ph.D. degree in VLSI Design from Anna University, Chennai India in 2014. She is working as an Associate Professor in Thiagarajar College of Engineering, Madurai since 2007. She teaches courses on system/digital and analog electronic design and VLSI processor architectures. Currently, five research scholars are doing their research under her guidance. She has authored or co-authored 42 international journal and conference papers like IET Circuits, Systems and Devices, Spinger, Wiley and Elsevier Publications. Also she has published 3 Books/Book Chapter in Springer LNCS and CCIS Publications. She has filed 2 Patent in BioMedical Engineering Field. She has guided the B.E students’ project which won the India Cadence Design Contest Award 2017 and 2018 instituted by Cadence Design System Pvt Ltd, Bangalore. In 2018, she was the technical program chair of the 22nd International Symposium on VLSI Design and Test. She is serving as a reviewer in IEEE Transaction on Nanotechnology, Elsevier and Inderscience Journals, respectively. Her research interests include RFIC Design, Physical Design Automation, Optimization Algorithms using Machine learning for IC and mixed signal circuits and systems for Bio-medical Devices.
I am a professor in the department of electrical and computer engineering at University of Cincinnati. My areas of expertise are: CMOS, Beyond-CMOS devices such as RRAM, FeFETs, gated-RRAM, TFTs, novel device design, fabrication, and testing, neuromorphic computing, and hardware security.
I am a Graduate Research Assistant at the University of Tennessee Knoxville, pursuing the PhD degree in Mixed-Signal Analog Circuit design.
Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.
Researcher, thinker, innovator, amateur, and little science... God almighty believed
I am designed mixed signal ICs for Music, Audio, IoT and sensor applications.
Dad. Partner. Scientist. Activist. Maker. — He/His
For most of my career, I was a CAD technology innovator and CAD system architect at Intel Corporation. I signed up recently for a Udemy class called "VSD - Making the Raven Chip: How to Design a RISC-V SoC." The class pointed me to Efabless.
R&D Engineer, interest in synthesis and verification software for electronics and photonics hardware
Amel is an Digital IC designer interested , used to work on HDL based Design for testability, Formal verification of Semi custom and IP based SOC DFT. Currently, working on IC design for Reliability. She designed a Test structures chip for Bias Temperature Instability characterization and analysis using TSMC 180nm Technology.
I would like to improve the tooling for open ASIC development and education with Rudder: https://github.com/0x01be/rudder
PhD Student @ UC Berkeley, formerly SWE @ Google
ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.
Engineer / VP
founder of patho.ai, using latest ai tech to accelerate pathology and drug discovery research using custom HDL HPC computation power of performing insilico simulation and compounds search and discovery.
Hi , I am Gajanan Chavan I am a passionate individual with a deep love for computers. My skills encompass C++, HTML, CSS, Bootstrap, Python programming, and data structures. Currently, I am pursuing a degree in Electronics and Telecommunication at SGGSIE&T in Nanded, Maharashtra. My goal is to continuously enhance my knowledge and expertise in the field of computer science and contribute to innovative projects and solutions. I am eager to connect with like-minded professionals and explore opportunities that allow me to apply my skills and contribute to the ever-evolving world of technology.
RTL design engineer with experience developing mobile GPUs (Samsung), high-end networking ASICs (Juniper) and CPU cores (MIPS). Co-author of lab manuals and online courses on FPGA design, RTL2GDSII flow and computer architecture. Founder of Verilog Meetup, a Silicon Valley and online community that develops open-source SystemVerilog examples targeting three niches: beginners, students who want to prepare for microarchitectural job interviews and university professors who want to avoid FPGA vendor lock (our examples are interoperable between Xilinx, Altera, Gowin and Lattice and compatible with ASIC flows, such as TinyTapeout and eFabless (in progress)).
Product design and development
Based in India, developing a new SoC type.
From Mining Gems in the field to mining data about gems and developing bleeding edge Gemological/Geological/Geophysical/Geochemical/Geospatial/Spectroscopic and other Survey, Testing, Measuring, Databasing, Retrieval, and Analytical Devices/Software/Tradecraft as well as beyond crystal unit level precision automated faceting/cutting/polishing/cabbing/carving/lapidary instruments and even 500 picometer diameter diamond polish... I do it all. Anyone in the industry wanting to spice up and drastically increase the efficiency and ROI on their wafer lapping/polishing capabilities: help me...help you...get ahead of the EUV/DUV/3nm and finer processes (my system has an RI value of less than 500pm... THAT is smaller than 8 carbon atoms in a cubic formation...carbon...not silicon...
Senior lecturer at Vasyl Stefanyk Precarpatian National University
Senior security researcher, compiler/binary hacker, NFC ninja, hardware hacker with a FPGA hammer. Previously Pay Security.
Learning to build brain-inspired Neuromorphic chips. I used to wrestle with GPUs for graphics and AI. Previously at Unity Technologies and Electronic Arts.
I am a highly skilled and motivated Integrated Circuit (IC) Designer with expertise in both schematic and layout design and verification. Throughout my career, I have played a key role in the development of multiple image sensor Readout Integrated Circuits (ROICs), from initial concept to final production. My key strengths include: • Schematic Design and Verification: I have extensive experience in designing and verifying top-level schematics and novel digital IP blocks for ROICs. I am proficient in using Verilog-A, PWL models, and SPICE netlists for comprehensive validation. • Layout Design and Verification: I possess a strong understanding of physical design principles and a proven track record of owning physical design for complex ROICs, including floor planning, top-level integration, and signoff. I have expertise in 3D IC integration and have developed reusable block-level layouts for various digital and analog IPs. • Design Enablement: I am passionate about creating efficient design flows. I have pioneered an open-source digital design flow and a TSV routing flow, established methodologies for 3D IC validation, and customized Calibre rules for advanced designs. I am a results-oriented individual with a keen eye for detail and a passion for innovation. I am proficient in various EDA tools and PDKs and possess excellent problem-solving and analytical skills. I am eager to contribute my expertise to a team that is developing cutting-edge imaging technologies
Open Hardware Scientist
Optimisation experience spanning more than 30 years for software, 25 years for cryptography, and 13 years for hardware. Background in Physics, Pure and Applied Mathematics, and Computer Science (PhD in Cryptology).
Since 2001 I have worked for a small IC Layout design firm located in Wilsonville, Oregon called Coast-to-Coast Layout Design Inc. We provide full-custom mask design services to big semiconductor partners, both digital and analog/mixed-signal. I began my career as a part-time Linux systems administrator, and was taught mask design by my mentor and boss, then over the past couple decades I moved up the ranks to my current GM position where I am responsible for most day-to-day operations and management of multiple mask design teams who are very highly valued by our customers that rely on our services to meet tough tapeout schedule and quality requirements. I'm here because I'm planning to use open-source EDA tools to help train new mask designers to help grow my company.
