semi retired, small startup for Medical (oncology/treatment) system, analog circuit designer, College Lecturer, Surfer&moto Rider.
I'm an experienced Analog Mixed Signal IC design engineer with 20+ years of experience in Analog IC level design, analog system modeling, layout, and lab testing. Areas of expertise are SerDes, ADC, DAC, PLL, RF , Base Band, Band Gap, Opamps.
IC Design Engineer
Associate professor at Pontificia Universidad Catolica de Chile, analog and mixed-signal design
I am researcher with goals of developing high end technologies for the future.
Lecturer UiTM
Self-taught Electronic Engineer with a lot of experience in programming. I consider myself creative, analytical and dynamic, through my studies I have developed the ability to face and lead changes; I am interested and committed to continuous improvement in a globalized world, both professionally and personally. Being able to contribute what I have learned and add value, thus learning from the opportunities in today's working world.
A researcher and VLSI guy
I am VLSI Trainee wanted to design chips
ECE Undergraduate Student @ Guru Gobind Singh Indraprastha University
Experienced Senior Design Engineer with a demonstrated history of working in the electrical and electronic manufacturing industry. Skilled in DAC, SPICE, ADCs, Electronics Hardware Design, and Management. Strong engineering professional with a M-Tech focused in VLSI System Designs from Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering &Technology and also a B-Tech Degree in the field of Electrical, Electronics and Communications Engineering from Mahatma Gandhi Institute of Technology.
Assistant Professor at the Mechanical and Aerospace Engineering Department. The Henry Samueli School of Engineering. University of California, Irvine.
I am an Assistant Professor in the VLSI vertical of Department of ECE at RV College of Engineering, Bengaluru, Karnataka. I am a passionate teacher who teaches various courses in VLSI domain. My research interests are in the areas of Analog and RFIC Design. I got several opportunities at RVCE to implement various personalized teaching methods for the students, facilitated experiential learning, adapted innovative techniques in teaching and learning through flipped classroom and blended learning approaches. I am currently responsible for the curriculum design and development for courses in VLSI domain. I am also responsible for introducing new electives in specific areas. I have a YouTube channel with 300 + videos on the courses taught so far for the benefit of a wider student community.
D Gracia Nirmala Rani received the B.E. degree in Electronics and Communication Engineering from Syed Ammal Engg College, Madurai, India, in 2004, and M.E. degree in VLSI Design from Karunya University, Coimbatore, India in 2007. She has awarded Ph.D. degree in VLSI Design from Anna University, Chennai India in 2014. She is working as an Associate Professor in Thiagarajar College of Engineering, Madurai since 2007. She teaches courses on system/digital and analog electronic design and VLSI processor architectures. Currently, five research scholars are doing their research under her guidance. She has authored or co-authored 42 international journal and conference papers like IET Circuits, Systems and Devices, Spinger, Wiley and Elsevier Publications. Also she has published 3 Books/Book Chapter in Springer LNCS and CCIS Publications. She has filed 2 Patent in BioMedical Engineering Field. She has guided the B.E students’ project which won the India Cadence Design Contest Award 2017 and 2018 instituted by Cadence Design System Pvt Ltd, Bangalore. In 2018, she was the technical program chair of the 22nd International Symposium on VLSI Design and Test. She is serving as a reviewer in IEEE Transaction on Nanotechnology, Elsevier and Inderscience Journals, respectively. Her research interests include RFIC Design, Physical Design Automation, Optimization Algorithms using Machine learning for IC and mixed signal circuits and systems for Bio-medical Devices.
I am Dr. Naushad Alam working as an Associate Professor in the Department of Electronics Engineering, Z H College of Engineering & Technology, Aligarh Muslim University, Aligarh, India. I received B. Tech. degree in Electronics & Communication Engineering from Jamia Millia Islamia, New Delhi in 2003, and M. Tech. Degree in Electronic Circuits & Systems Design from Aligarh Muslim University, Aligarh in 2009. I earned Ph.D. degree in Microelectronics from Indian Institute of Technology Roorkee, India in 2013. My doctoral work was on nanoscale circuit design considering the impact of process-induced mechanical stress. He has published 29 papers in SCI indexed journals that include 10 IEEE Transactions and 33 papers in reputed conferences. I have supervised two PhD thesis in the area of device-circuit co-design and presently supervising two more PhD students. I have also successfully executed a UGC funded research project on TFET based SRAM cell design for IoT Applications. My research interests include device-circuit co-design, robust nanoscale circuit design, low power circuit design, PVT tolerant circuit design, Near-Threshold/Sub-Threshold circuit design etc.
Mixed-signal designer
Hi, I'm a student at UACJ and I like integrated circuit designs.
An energetic semiconductor professional with varied experience in the field of research, teaching and IC design. 📌 More than 6 years of experience in analog and mixed signal IC design. 📌 3 years of mentoring experience in analog circuit and layout design. 📌 Been part of the 4 complete IC development project. 📌 Inventor and co-inventor of 2 patents (filed) in the field of high-speed data path communication. 📌 Published few research papers with more than 30 engineering citations. 📌 6 month experience as a lead role in standard cell library development in a leading semiconductor organisation. 📌 more than 4 years of teaching experience in under-graduate electronics engineering courses.
Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.
President and CEO
Analogue Circuit Designer
Electrical engineer with interests in ASIC design, biomedical imaging, and scientific instrumentation.
Working on a PhD in electronics and nanofabrication at the University of Glasgow. Interested in designing CPUs and SoCs with RISC-V.
I am a professor at Federal University of Juiz de Fora (UFJF). I'm interested on analog and mixed-signal integrated circuits, as well as analog and digital electronics and microprocessors.
A bit of everything - mostly focused on networking system level designs / FPGA / Switch Fabric from concept to validation - and now automotive
Enthusiastic VLSI Design Engineer currently working in Domain Specific Architectures
Designer specialized on VLSI radiation tolerant architectures and circuits
I'm the CEO of a fabless semiconductor start-up company and have more than 15 years experience in designing mixed-signal ASICs on various foundry processes.
Research scientist working in a MOS technology support for teaching at academic institutions.
Jack of all trades
Analog and Mixed signal IC designer
To obtain a challenging position as a VLSI Engineer in a reputable organization where I can utilize my skills and knowledge to contribute to the growth of the organization while also enhancing my own personal and professional development.
Hugo Hernández received his B.S. degree in Electronic Engineering from The Industrial University of Santander, Colombia in 2005 and M.S. degree in Electrical Engineering from Polytechnic School of the University of São Paulo (EPUSP), Brazil in 2008. Hugo obtained his Ph.D degree in Electrical Engineering from University of São Paulo in 2015. Hugo is an Analog/Mixed‐signal design engineer with strong background in IC design techniques, industry experience on ASICs for sensoring applications and hands on experience in 28nm, 55nm, 65nm, 130nm, 180nm and 0.35um CMOS process nodes. Research interests include Low power Data Converters, SAR ADCs, DACs, PLLs and Low power analog design.
ASIC Designer with experience in Back-end & Front-end stages for ASIC design flow.
B. Tech from IIT Bombay 73 elec and Masters from Philips Holland 75 and working on design and development 1975 till date
From Mining Gems in the field to mining data about gems and developing bleeding edge Gemological/Geological/Geophysical/Geochemical/Geospatial/Spectroscopic and other Survey, Testing, Measuring, Databasing, Retrieval, and Analytical Devices/Software/Tradecraft as well as beyond crystal unit level precision automated faceting/cutting/polishing/cabbing/carving/lapidary instruments and even 500 picometer diameter diamond polish... I do it all. Anyone in the industry wanting to spice up and drastically increase the efficiency and ROI on their wafer lapping/polishing capabilities: help me...help you...get ahead of the EUV/DUV/3nm and finer processes (my system has an RI value of less than 500pm... THAT is smaller than 8 carbon atoms in a cubic formation...carbon...not silicon...
Senior lecturer at Vasyl Stefanyk Precarpatian National University
Adjunct Professor and Chief Mentor, Advanced VLSI Lab Silicon University, Bhubaneswar, India
I am a highly skilled and motivated Integrated Circuit (IC) Designer with expertise in both schematic and layout design and verification. Throughout my career, I have played a key role in the development of multiple image sensor Readout Integrated Circuits (ROICs), from initial concept to final production. My key strengths include: • Schematic Design and Verification: I have extensive experience in designing and verifying top-level schematics and novel digital IP blocks for ROICs. I am proficient in using Verilog-A, PWL models, and SPICE netlists for comprehensive validation. • Layout Design and Verification: I possess a strong understanding of physical design principles and a proven track record of owning physical design for complex ROICs, including floor planning, top-level integration, and signoff. I have expertise in 3D IC integration and have developed reusable block-level layouts for various digital and analog IPs. • Design Enablement: I am passionate about creating efficient design flows. I have pioneered an open-source digital design flow and a TSV routing flow, established methodologies for 3D IC validation, and customized Calibre rules for advanced designs. I am a results-oriented individual with a keen eye for detail and a passion for innovation. I am proficient in various EDA tools and PDKs and possess excellent problem-solving and analytical skills. I am eager to contribute my expertise to a team that is developing cutting-edge imaging technologies
