Efabless Logo

Tag Search

"profiles" search for "skills": ICC
Open Search

Number of Results: 11

entry image

Andre5

I am Electronic Engineer from Chile, I like DSP and radioastronomy applications an ordinary guy

Skills

C/C++ System Verilog Verilog Design Compiler Descartes Formality ICC ICC2 DFT Xilinx ISE design suite FPGA full flow programming

Area of Expertise

Circuits: Filters Circuits: Signal Processing Digital: Placement and Routing System: FPGA Programming System: Quality Assurance System: Test Programming
entry image

kartik dev pujari

i have done PGDMA in ASIC Design in physical design domain , from RV-VLSI Bangalore.

Skills

icc primetime cts sta floorplanning power analysis tcl

Area of Expertise

PNR
entry image

Arun Kumar V

4+ years of VLSI Backend experience. Working as Physical Design Engineer. Expertise in Analog layouts, physical verification and Physical Design. Open to learn and explore other domains of VLSI design.

Skills

Genesys ICC Tcl/Tk

Area of Expertise

Analog: Layout CAD: Scripting Digital: Placement and Routing
entry image

Ahmed Ramzy

Skills

C/C++ Octave System Verilog Tanner L-Edit Verilog VHDL ICC DC

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis
entry image

B Mallu

Skills

ICC2

Area of Expertise

Digital: Placement and Routing
entry image

Abdelrahman Ruby

St. ASIC Physical Design Engineer

Skills

Cadence Virtuoso Tcl/Tk Verilog VHDL icc

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis
entry image

Jerry Yin

Skills

Cadence Virtuoso Calibre Magic CAD Verilog Cadence Innovus Synopsys Design Complier Synopsys ICC2 Synopsys Prime Time

Area of Expertise

Academic: Student VLSI Physical Design
entry image

Atul Agarwal

Skills

Calibre ICC2 Innovus Machine learning PrimeTime Tweaker

Area of Expertise

Digital: Placement and Routing
entry image

Nandhini Jayapandian

Skills

Verilog Synopsys DC Synopsys ICC Synopsys ICC2 RedHawk

Area of Expertise

VLSI
entry image

Likhit Daggubati

Skills

Perl Python Tcl/Tk Verilog Synopsys DC Synopsys ICC2 Synopsys PT Synopsys StarRC-XT

Area of Expertise

Digital: Synthesis SoC: Floorplanning System: Chip Editing
entry image

Mohammed Salah

Experienced ASIC Digital Design and Physical Implementation Enthusiast

Skills

Cadence Encounter Tcl/Tk Verilog Synopsys Design compiler (DC) Synopsys Formality Synopsys ICC Synopsys ICC II Synopsys PrimeTime QuestaSim Vivado

Area of Expertise

Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis