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"profiles" search for "area_of_expertise": System: Chip Editing

Number of Results: 36

David Garner

An experienced mixed-signal IC design engineer / design manager with over 25 years experience. Has design and led the design of multiple mixed-signal ICs through to tapeout and silicon verification. Also experienced with the delivery of IP blocks. Worked across multiple market sectors.

David Rees



Area of Expertise

System: Chip Editing

Mark Anderson

Current iOS Programmer, EE with decade of physical design experience in mixed signal - worked on POWER architecture PLLS.

veena S Chakravarthi

SoC Architect.Technologist. Hands-on experience in complex low power SoC designs, from concept to production. Excellent track record in successful development and production of ASICs, Technologies: Bluetooth, WLAN, IoT, Gigabit Ethernet, EPON networks, Interface ICs, Broadcast TV and Communication controllers. Demonstrated consistent track record of first-pass silicon success. PhD in Low power VLSI. Recipient of US and Indian patents. Core Competency: Chip Architecture, Micro Architecture, logic design, RTL Verilog coding, Chip level verification, Static Timing analysis, Formal Verification, design rule checking, AXI, AHB and APB bus protocols, Digital ASIC methodology, DFT methodology, Low Power ASIC design, Interfacing with backend teams, Timing closure, Post silicon bring up and validation, Project Planning, Scheduling and Management, FPGA Prototyping. Author of Book "A Practical Approach to VLSI System on Chip (SoC) Design" published by Springer Nature. Domain experience: Communications, EPON, WLAN, Bluetooth, IoT, Healthcare, Nextgen TV, Automotive. Managed dynamic, cross cultural teams of size 40 to 100. Standards worked on IEEE802.3, IEEE802.11b, ac, ad. ATSE 3.0, Automotive ethernet, Bluetooth Quality standards: ISO 9002, ISO 13485, IEC 60601-2 Funded Research: Derivative Low power standard cell library development PhD Guidance: 2 one in Asynchronous VLSI design methodology and second in Sub 1V power supply for complex SoCs. Co-founded healthcare company:Sensesemi Technologies Pvt. Ltd. Academic research head and taught engineering students for their undergrad, Post grad and PhD courses Chair, IEEE NanoTechnology Council, Bangalore Section as a founder Chairperson, Current Senior IEEE member.

Sai Ritish G

Just an average engineering student

Ignacio Herrera

I am a PhD. Telecommunication Engineer with 25 years of working experience in the industry. I started my career in 1997 as an IC Design Engineer, then I moved to other technical and management roles in the semiconductor and aerospace industries. Since 2017 I am also teaching IC Design at University for MsC. graduate students.

Zhiyang Ong

Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.

Milind Potdar

Microelectronics Enthusiastic, Vast experience in embedded design for various domains.