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"profiles" search for "area_of_expertise": SoC: ESD

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Number of Results: 40

Philipp Gühring

I am a software developer, trying to learn about hardware design

Skills

C/C++ Circuit Design Magic CAD ngspice Perl Python Software Developer Tcl/Tk Verilog

Area of Expertise

Business: PCB Manufacture CAD-Dev CAD: Scripting CAD: Tool Development Cryptography Miscellaneous: Cryptography Miscellaneous: Neural Networks Security SoC: ESD System: PCB

Mohamed Bamakhrama

Skills

C/C++ Python System Verilog System-C Verilog VHDL

Area of Expertise

Digital: RTL SoC: ESD

jatindersingh

Skills

Analog/Digital Circuit Design C/C++ Electric CAD Magic CAD ngspice Python System Verilog System-C Tcl/Tk Verilog VHDL VLSI/ASIC and SoC Development

Area of Expertise

Analog-SMPS Analog: Simulation Analog: Verification Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital-DV Digital-RTL Digital: DFT Digital: Placement and Routing Miscellaneous: Neural Networks SOC-DV SoC: ESD SoC: Floorplanning SoC: Verification System-DSP System: Chip Editing System: FPGA Programming

Luc Wong

I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".

Skills

C/C++ Cadence Encounter Cadence Virtuoso Eldo Matlab Perl Python Software Developer Spectre SPICE Opus System Verilog Tcl/Tk Verilog VHDL

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Neural Networks SoC: ESD SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: PCB System: Power Integrity System: Signal Integrity System: Test Equipment System: Test Programming

Salvatore M. Cherchi

Skills

C/C++ Eagle CAD Electric CAD Matlab ngspice Python System Verilog

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Business: Design Services Circuits: Communication Circuits: Memory Circuits: Signal Processing Miscellaneous: Cryptography SoC: ESD SoC: Floorplanning System: Fabrication Process System: Power Integrity System: Signal Integrity

Camillo

Experienced Analog Design Engineer with strong background in HV CMOS ASICs.

Skills

C/C++ Cadence Virtuoso Calibre Matlab Octave Perl Python SKILL Spectre

Area of Expertise

Academic: Research Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Circuits: Power Management SoC: ESD SoC: Floorplanning System: PCB

Pengyu Wei

Skills

Cadence Virtuoso Matlab Octave

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling SoC: ESD System: PCB System: Test Equipment

Menaka Sajjan

Skills

Cadence Encounter Cadence Virtuoso Perl Verilog VHDL

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: ESD

MAYANK VASHISHT

Interested in Design, Verification, and Hand-off of Analog IPs. Worked on the definition, modeling, design, verification of DC-DC converters, Chargers, Ideal-Diodes, LDOs, Regulators, Bandgap references, Current limiting and sensing architectures. Excited for challenges in Analog Design, Layout and Post-silicon verification.

Skills

Cadence Virtuoso Matlab Octave SKILL Spectre System Verilog Verilog

Area of Expertise

Analog: Design Analog: Modeling Analog: Simulation Analog: Verification Circuits: Filters Circuits: Power Management Circuits: Signal Processing Digital: Verification SoC: ESD System: Test Programming

Azhar Din

Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.

Skills

Cadence Virtuoso Calibre Diva Leadership Matlab Perl Spectre

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Management CAD: Scripting Circuits: Communication Circuits: Filters Circuits: Power Management Circuits: Sensors SoC: ESD SoC: Floorplanning SoC: Verification System: Fabrication Process System: PCB System: Test Equipment

David Garner

An experienced mixed-signal IC design engineer / design manager with over 25 years experience. Has design and led the design of multiple mixed-signal ICs through to tapeout and silicon verification. Also experienced with the delivery of IP blocks. Worked across multiple market sectors.

Skills

Cadence Virtuoso Diva Leadership Matlab Octave SKILL Spectre

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Management Business: Patents Circuits: Communication Circuits: Filters Circuits: Power Management Circuits: Sensors Circuits: Signal Processing SoC: ESD SoC: Floorplanning SoC: Verification System: Chip Editing System: Fabrication Process System: Power Integrity System: Quality Assurance System: Signal Integrity System: Test Equipment

Amit Prakash Gonnagar

Skills

Cadence Encounter Cadence Virtuoso Calibre Electric CAD Magic CAD ngspice Perl Spectre System Verilog Tcl/Tk Verilog

Area of Expertise

Circuits: Power Management Digital: Placement and Routing Digital: Synthesis SoC: ESD SoC: Floorplanning System: Chip Editing System: Fabrication Process System: PCB System: Power Integrity System: Signal Integrity System: Test Programming

Lakshya Kailkhura

Skills

Cadence Encounter

Area of Expertise

CAD: Scripting Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification SoC: ESD SoC: Floorplanning System: Signal Integrity

Shinya Takeuchi

I like to make toys like flapping planes.

Skills

C/C++ Cadence Encounter Cadence Virtuoso Perl

Area of Expertise

Analog: Layout SoC: ESD

Tony Chan

30+ years in IC design, completed several NOR/NAND flash projects, and running in production.

Skills

Cadence Virtuoso Calibre Leadership Python

Area of Expertise

Circuits: Memory SoC: ESD SoC: Floorplanning

zhang xin

Skills

Cadence Virtuoso Calibre Hercules Perl Spectre

Area of Expertise

Analog: Layout Analog: Modeling Analog: Simulation Business: Design Services Business: Foundry Services CAD: Scripting CAD: Tool Development SoC: ESD SoC: Floorplanning SoC: Verification

Charles Hu

RF/Analog IC design and SOC

Skills

Cadence Virtuoso Calibre Python System Verilog RF EMX ADS

Area of Expertise

Analog: Design Analog: Simulation Business: Design Services Business: Packaging Circuits: Communication Circuits: Power Management SoC: ESD SoC: Floorplanning System: Test Equipment System: Test Programming

Krishna Sai Kanthan

Skills

C/C++ Cadence Virtuoso Perl System Verilog Tcl/Tk Verilog vim

Area of Expertise

Digital: Placement and Routing SoC: ESD System: Power Integrity

Jerry Cheng

Skills

Cadence Encounter Calibre Perl Python Tcl/Tk Verilog VHDL

Area of Expertise

CAD: Scripting Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: ESD SoC: Floorplanning System: Power Integrity

bill rivard

I am interested in new things. I've designed chips from definition to polygons, mostly in the pursuit of new capabilities.

Skills

Magic CAD spice Verilog

Area of Expertise

Academic: Research Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Business: Management Business: Patents Circuits: Power Management Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography Miscellaneous: Neural Networks SoC: ESD SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: PCB System: Signal Integrity

Abdul Wadood

Final year student of Electrical Engineering at UET Lahore. Area of expertise is Digital Design, Computer Architecture and SOCs.

Skills

Python System Verilog Verilog

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: ESD

Sharath Hariharapura Subashchandra

Skills

Calibre Hercules Magic CAD Netgen Tcl/Tk Verilog VHDL

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: ESD SoC: Floorplanning System: Fabrication Process

Nagaraj Ananthapadmanabhan

Skills

Cadence Encounter Cadence Virtuoso Leadership Matlab Python Spectre Tanner L-Edit Verilog VHDL

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Management Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification SoC: ESD SoC: Floorplanning System: Fabrication Process System: Packaging System: PCB

Eric Fogleman

Skills

C/C++ Cadence Virtuoso Leadership Matlab ngspice Octave Python Spectre Tanner L-Edit Verilog

Area of Expertise

Analog: Design Circuits: Communication Circuits: Filters Circuits: Signal Processing Digital: RTL SoC: ESD SoC: Floorplanning

Kali_Core

electronic system designer / software and hardware engineer, embeded system expert, signal expert, proccess designer, researcher, Developer of complexity and reversal wantings. Reverse engineer. i addopt my whole life to this science. thank you for presentings of quantum, psych

Skills

C/C++ Cadence Virtuoso Eagle CAD Electric CAD Leadership Software Developer Spectre System Verilog System-C Verilog VHDL

Area of Expertise

Academic: Research Analog: Design Analog: Modeling Analog: Verification Business: Design Services Business: PCB Manufacture Business: Public Relations Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: RTL Digital: Synthesis Miscellaneous: Cryptography Miscellaneous: Neural Networks SoC: ESD SoC: Verification System: Chip Editing System: FPGA Programming System: PCB System: Signal Integrity System: Test Programming

Saroj Rout

Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.

Skills

Calibre Eagle CAD Magic CAD Matlab ngspice Octave Perl Python Scilab SKILL Spectre System Verilog Tanner L-Edit Verilog

Area of Expertise

Academic: Teaching Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services CAD: Scripting Circuits: Filters Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: RTL SoC: ESD System: PCB System: Signal Integrity System: Test Equipment System: Test Programming

harshitha yadavalli

Skills

Cadence Virtuoso System-C Verilog

Area of Expertise

Academic: Student Analog: Simulation Digital: RTL SoC: ESD

ROSHAN ALI SK

Skills

C/C++ Cadence Virtuoso

Area of Expertise

SoC: ESD SoC: Floorplanning SoC: Verification

Florian Ballenegger

Analog and mixed-signal IC designer.

Skills

C/C++ Cadence Virtuoso Calibre Matlab ngspice Python Spectre

Area of Expertise

Analog: Design Analog: Layout Analog: Simulation CAD: Scripting Circuits: Power Management SoC: ESD

Shivam Potdar

RISC-V Enthusiast GSoC 2020 @ FOSSi Foundation RA @ CAD Lab, IISc Bengaluru, India EE Senior @ NITK Mangalore, India

Skills

C/C++ Eagle CAD Matlab ngspice System Verilog Verilog c

Area of Expertise

Academic: Student CAD: Scripting Digital: RTL Miscellaneous: Neural Networks SoC: ESD System: FPGA Programming

Denise Cocco

President and CEO

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Eldo Matlab Perl Python SKILL Spectre SPICE Opus System Verilog Tanner L-Edit Verilog

Area of Expertise

Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Foundry Services Business: Packaging Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: Placement and Routing Digital: RTL SoC: ESD SoC: Floorplanning SoC: Verification System: Chip Editing System: Fabrication Process System: Packaging System: Quality Assurance

Mandala Sai Uthej

Skills

Verilog

Area of Expertise

Academic: Student Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: ESD SoC: Floorplanning System: Signal Integrity

Malcolm Smith

IC designer with more than 25 years post Ph.D. experience. Specialising in RF, RFIC, analog and mixed-signal. Wide experience in Architecture, system and circuit design. RF front-end module design for cellular with CMOS PA. Over 40 patents issued.

Skills

C/C++ Cadence Virtuoso Matlab Octave

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Circuits: Communication Circuits: Filters Circuits: Power Management Circuits: Sensors Circuits: Signal Processing SoC: ESD SoC: Floorplanning System: PCB

Gabriel Costa

I am an analog design engineer with over 10 years of experience. Most of designs lie in the field of power management (DC/DC converters), frequency synthesis (phase-locked loops), wireless power and data transfer (NFC front-ends as well as medical implants).

Skills

C/C++ Cadence Virtuoso Calibre

Area of Expertise

Academic: Teaching Analog: Design Analog: Layout Analog: Simulation Analog: Verification Circuits: Communication Circuits: Power Management Circuits: Sensors Circuits: Signal Processing SoC: ESD

Shaolin

Skills

C/C++ Leadership Matlab Python System Verilog System-C Verilog

Area of Expertise

Academic: Research Circuits: Microcontrollers SoC: ESD

Michael de Guzman

Skills

Cadence Virtuoso Leadership SKILL Spectre

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Management Circuits: Communication Circuits: Filters Circuits: Microcontrollers Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Miscellaneous: Cryptography SoC: ESD SoC: Floorplanning System: Quality Assurance System: Test Equipment

Anand Bariya

I have over thirty years of experience in the semiconductor industry, having worked in fab, EDA and design engineering. have built and led large, geographically distributed teams at a senior manager level. I am passionate about developing talent and skills, particularly in young people from socio-economically underprivileged backgrounds.

Skills

Leadership Perl

Area of Expertise

Academic: Teaching Business: Design Services Business: Management Digital: DFT Digital: Placement and Routing Digital: Synthesis SoC: ESD SoC: Floorplanning

Sai Srinivas TNS

VLSI DOMAIN SKILLS --------------------------- • Digital Electronics • HDL: Verilog • HVL: System Verilog • TB Methodology: UVM • Protocols: APB, UART, I2C, SPI • EDA Tools: Modelsim, Quartus Prime, Questasim. VLSI RTL SKILLS ---------------------- • Digital Skills : Combinational and Sequential circuits • FSM • Memories • Verilog : Data types • Operators • BA and NBA • Delays in Verilog • Begin-end and fork-join Blocks • System tasks and Function • Compiler directive • FSM Coding. VLSI VERIFICATION SKILLS ------------------------------------ • System Verilog HVL: Data Types • Memories • Interface • OOPS • Constraint Randomization • Threads • Functional coverage • CRCDV • SV Testbench (Hands on SV Testbench) • Universal Verification Methodology: UVM Objects and Components • UVM Factory • UVM Phases • UVM Configuration • TLM • Virtual Sequence and Sequencer • UVM Testbench (Hands on UVM Testbench).

Skills

Python System Verilog Tcl/Tk Verilog

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: ESD SoC: Verification

Geo Jo

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Diva Eagle CAD Eldo Electric CAD Hercules Leadership Magic CAD Matlab Netgen ngspice Octave Perl Python Scilab SKILL Software Developer Spectre SPICE Opus System Verilog System-C Tanner L-Edit Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research Academic: Teaching Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Foundry Services Business: Management Business: Marketing Business: Packaging Business: Patents Business: PCB Manufacture Business: Public Relations Business: Sales CAD: Scripting CAD: Tool Development Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography Miscellaneous: Neural Networks SoC: ESD SoC: Floorplanning SoC: Verification System: Chip Editing System: Fabrication Process System: FPGA Programming System: Packaging System: PCB System: Power Integrity System: Quality Assurance System: Signal Integrity System: Test Equipment System: Test Programming

Berna Ors Yalcin

Berna Örs received the Electronics & Communication Engineering degree and the MSc degree in 1995 and 1998, respectively, both from the Istanbul Technical University (ITU), Turkey. She received the Electrical Engineering degree in applied sciences from the Katholieke Universiteit Leuven, Belgium, in 2005. Currently, she is a Professor at ITU. Her main research interests include cryptography, embedded systems, and side-channel attacks.

Skills

C/C++ Matlab Verilog VHDL

Area of Expertise

Academic: Research Academic: Teaching Circuits: Microcontrollers Digital: RTL Digital: Synthesis Miscellaneous: Cryptography SoC: ESD System: FPGA Programming