Trained as a Software Engineer, i am an advocate for Libre Ethical Technology in business.
Silicon Design Engineer
I m the Account manager, at Adroitec Systems Pvt Ltd, we are providing physical design services
HW development engineer
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
IC Design Engineer
Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.
VLSI design project manager
Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.
Learner for life
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
Teaching assistant for ASIC/FPGA and digital ICs courses.
Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.
Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.
Physical Design Engineer
Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)
Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.
An experimental physicist through sensor and instrumentation development.
Umer Imran is eager to work in the field of Computer Architecture and Memory Consistency. He is currently working as a Design Verification Engineer at Lampro Mellon, a training firm with the vision to transform Pakistan’s talent pool into leaders of RISC-V based SoC design. He constantly aims to gain expertise in the various domains of SoC Design including IP Design, ASICs, and low power architectures.
Interested in Design, Verification, and Hand-off of Analog IPs. Worked on the definition, modeling, design, verification of DC-DC converters, Chargers, Ideal-Diodes, LDOs, Regulators, Bandgap references, Current limiting and sensing architectures. Excited for challenges in Analog Design, Layout and Post-silicon verification.
Principal Engineer at ONiO AS
I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.
ASIC architect and designer. Specialize in deep learning, video, image and signal processing, and compression. Professor of Electrical and Computer Engineering at The College of New Jersey.
Assistant Professor (IISc) | Ph.D. & S.M. (MIT) | B.Tech. (IIT-KGP)
Pursuing masters in VLSI at IIT INDORE.
I am working as Co-founder & CTO of Upplysning Robotics, which is focused on the development of biomedical devices like digital stethoscopes with built-in ECG and PCG, auto-detect heart irregular arrhythmias, and its flagship project is the design of artificial hearts and implants inside the human body and also Cardiac Robotics medicals devices
current Phd Student in UCSC Hardware System Collective group formerly worked in Qualcomm Wireless R&D team as a design verification engineer
Kashif Inayat currently working as a doctorate fellow researcher at System-on-Chips (SoC) Laboratory, Electronics Engineering Department of Incheon National University, South Korea. He considers himself fortunate to have the opportunity to work under Prof. Jaeyong Chung at Incheon National University. Prior to starting his Ph.D., he completed his Master of Science in Electronics and Computer Engineering (ECE) from graduate school, Hongik University in 2019 under the supervision of Prof. Seong Oun Hwang. Moreover, during MS studies he worked at Information Security and Machine Learning Lab, Hongik University, South Korea as a graduate researcher for 2.5 years. Furthermore, he chaired the special sessions at International Conference on Green and Human Information Technology (ICGHIT 2019), held in Kuala Lumpur, Malaysia (Jan, 16-18, 2019). Moreover, he is a registered member of the Pakistan Engineering Council and a reviewer for the IEEE Access Journal.
Postgraduate student at IIT INDORE
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
Experienced SW developer (C/C++/C#) and digital HW designer (SoC/FPGA)
Currently working as a Graduate Instructor in the department of Electrical and Computer Engineering and pursuing my Ph.D. in Electrical Engineering at the University of Missouri-Columbia. My research focuses on the development and design of low power decision-making Integrated Circuit (IC) using different type of Ai/Machine-Learning techniques. Besides researching on developing future technology, I'm also a professionally trained Vocalist in traditional South-Asian music majoring in Tagore and have experience in freelancing of 5 years in Digital Art and Graphics.
PhD student working on a superconducting FPGA design aiming to work on neuromorphic computing in the future.
working as Assistant Professor in Sree Vidyanikethan engineering college, Tirupati.
SoC Architect.Technologist. Hands-on experience in complex low power SoC designs, from concept to production. Excellent track record in successful development and production of ASICs, Technologies: Bluetooth, WLAN, IoT, Gigabit Ethernet, EPON networks, Interface ICs, Broadcast TV and Communication controllers. Demonstrated consistent track record of first-pass silicon success. PhD in Low power VLSI. Recipient of US and Indian patents. Core Competency: Chip Architecture, Micro Architecture, logic design, RTL Verilog coding, Chip level verification, Static Timing analysis, Formal Verification, design rule checking, AXI, AHB and APB bus protocols, Digital ASIC methodology, DFT methodology, Low Power ASIC design, Interfacing with backend teams, Timing closure, Post silicon bring up and validation, Project Planning, Scheduling and Management, FPGA Prototyping. Author of Book "A Practical Approach to VLSI System on Chip (SoC) Design" published by Springer Nature. Domain experience: Communications, EPON, WLAN, Bluetooth, IoT, Healthcare, Nextgen TV, Automotive. Managed dynamic, cross cultural teams of size 40 to 100. Standards worked on IEEE802.3, IEEE802.11b, ac, ad. ATSE 3.0, Automotive ethernet, Bluetooth Quality standards: ISO 9002, ISO 13485, IEC 60601-2 Funded Research: Derivative Low power standard cell library development PhD Guidance: 2 one in Asynchronous VLSI design methodology and second in Sub 1V power supply for complex SoCs. Co-founded healthcare company:Sensesemi Technologies Pvt. Ltd. Academic research head and taught engineering students for their undergrad, Post grad and PhD courses Chair, IEEE NanoTechnology Council, Bangalore Section as a founder Chairperson, Current Senior IEEE member.
I am a PhD student at National University of Sciences and Technology, Islamabad
I am professor at Dept of EEE, BUET, Passionate to teach students IC Design and Fabrication Skill.
Hardware Systems Architect at AroLeap
Digital and Mixed Signal Verification Engineer, with 9+ years of industry experience, looking to explore the entire chip design cycle.
Master's research student in IC design has hands-on experience on Cadence tools like Virtuoso, Genus, Innovus, Calibre. Motivated to learn more in the field of IC design
I am a Senior Undergraduate in Electrical Engineering Department at IIT Gandhinagar, India. VLSI Design and the ability to tweak at the hardware level interest me a lot!
Cryptography and security researcher at Seagate Technology
ASIC and FPGA design and verification Engineer with a sideline in bring devops to Hardware projects
I am a student in my final year of B.tech in electronics. I am eager to learn about vlsi and its technology. I want to take part in openMPW program
Just another big dreaming engineer with a desire to learn silicon microfab
Received B.S. degree from Electrical and Electronics Engineering in Middle East Technical University, Turkey, in 2019. Currently, pursuing M.S. degree from Electronics Engineering in Bogazici University, Turkey. Research interests are computer architecture, hardware security and secure memory architecture
Chip Design CAD Expert
I am interested in new things. I've designed chips from definition to polygons, mostly in the pursuit of new capabilities.
Dad. Partner. Scientist. Activist. Maker. — He/Him
I am an Electronics Engineer now continuing my MS in electronics from COMSATS Abbottabad in Analogue Chip Design.
Final year student of Electrical Engineering at UET Lahore. Area of expertise is Digital Design, Computer Architecture and SOCs.
ASIC Verification Engineer with 12+ yrs of exp.
IC design Engineer
Electrical Engineering student at UFMG, scheduled to graduate in Dec/2022. Experience in the automotive sector by the Formula Tesla UFMG team, designing electrical and electronic systems. Exchange experience in South Africa for 3 months studying English and working voluntarily in needy settlements. Currently, work as Software Engineer at Cadence Design Systems.
Hon-Piu Lam, is a Ph.D. candidate in the Department of Electronic and Computer Engineering of the Hong Kong University of Science and Technology (HKUST). He was an analog IC designer engineer in Valence Semiconductor from 2004 to 2007. From 2007 to 2015, he joined Fujitsu Semiconductor focusing on the embedded NOR flash design. He has been a researcher in HKUST focusing on the integrated power electronic and data converter. His research interests include readout electronics, integrated power electronics and radiation hardened electronics for experimental physics.
I am a Masters fellow student of RFCS2 Lab in IC Designing.
Automation enthusiast (likes to code in Perl). At this time, Doing Master's in VLSI Design and working as an intern @intel. Great learning experience doing both simultaneously. Have experience designing in both circuit (Low power & timing) & device level (high performance designs for digital applications). Obtained honor of 3rd position in concept design competition by ISRO for designing temperature & radiation resistant Tunnel FET. Would love to work with all device technology enthusiasts as opportunities arise.
Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.
Mixed-signal designer
Innovative developer with recognized success at designing, testing, implementing and maintaining computer hardware and software. Critical thinking and forward-focused professional coding in various programming languages. Delivers clear and engaging communications to colleagues and customers and inspires enthusiasm for engineered products and systems.
I'm a new grad Digital Design engineer working. Looking forward to contribute to open source silicon projects.
Independent Digital Design and Verification Expert with more than 20+ years of experience and founder of semify. While working for established semiconductor companies like Infineon, Dialog Semiconductor and NXP I was responsible for bringing ideas into working ASICs. I developed USound’s first ASIC from FPGA based prototyping to tapeout with minimal resourcing, demanding timeline and tight area and power consumption constraints. Currently I'm acting as a consultant for easyIC and Cypress / Infineon. In addition I'm is also lecturer at the FH Joanneum Graz and guest lecturer at the Technical University Graz.
Silicon Entrepreneur with extensive experience in Digital Physical Design, EDA and HPC Infrastructures for Electronic Design.
Hello I am Rakesh , I am pursuing my Under Graduation in Electronics and Communication Engineering at KLE Technological University, Hubballi. I am looking ahead work in Digital VLSI Domain. :D
R&D Engineer
An analog mixed-signal circuit designer for low-power precision sensor interfaces. See https://staff.aist.go.jp/ippei.akita/
Dad. Partner. Scientist. Activist. Maker. — He/His
Research Associate at Micro Electronics Research Lab (MERL) working as a hardware design engineer.
I'm a PhD student working to make mixed-signal chip design more accessible, drawing inspiration from software development techniques. Prior to starting the PhD program, I spent a number of years working in industry at both the chip- and PCB-level on optical sensors and power systems.
I am currently working as a Research Associate. We are doing research and development on RISC-V Technology.
I'm a Senior Researcher at the Barcelona Supercomputing Center and Junior Faculty at Polytechnic University of Catalonia (UPC). I'm the recipient of the RISC-V Educator of the Year Award 2019, for the advanced graduate course Processor Design I'm teaching at UPC, which is focused on the design of high-performance safety-critical systems. I'm the PI of the GPU4S project funded by the European Space Agency (ESA) in which we are investigating the applicability of embedded GPUs in space.
Digital Systems and Software Engineer (formerly in management VP and Director of engineering).
Research Associate at MERL mainly focusing of firmware and driver development for SoCs.
I am a final year B.Tech undergrad from India highly passionate about digital system design.
I am accomplished digital design engineer having 8 years of industrial expertise . I am currently working on IP design and IP integrations stuffs .
Osaze Shears is passionate about many engineering and computational concepts. These include embedded systems, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and microprocessor technologies. Osaze spends his free time tutoring other students who are interested in learning to become better computer scientists and engineers to benefit the greater society. Osaze is currently a PhD student at Virginia Tech conducting research under the Multifunctional Integrated Circuits and Systems (MICS) lab. His research interests include: • Spiking Neural Networks • Hardware Acceleration • SoC Design with ASICs and FPGAs • Deep Learning • Edge Computing
ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.
Designer specialized on VLSI radiation tolerant architectures and circuits
I've done everything from silicon design at the "bottom of the stack" to System Architecture and Design (with plenty of SW to go with it; at every level)
I am a senior ASIC and IP development person. My strength is in building high performance ASIC teams that deliver high quality ASIC and IP products .
A software developer, technology manager, and hardware tinkerer aspiring to imbue slices of crystals with intelligence.
I'm an ASIC Design Engineer with a focus on SoC verification. With over three years of experience in the field, I have had the privilege of successfully completing and taping out three projects. My expertise lies in ensuring the functionality and performance of complex System-on-Chip designs through thorough verification methodologies. Throughout my career, I have gained a deep understanding of the entire design flow, from specification and architectural exploration to RTL coding and verification. I am proficient in industry-standard verification languages and methodologies, such as SystemVerilog and UVM.
Berna Örs Yalçın received the Electronics & Communication Engineering degree and the MSc degree in 1995 and 1998, respectively, both from the Istanbul Technical University (ITU), Turkey. She received the Electrical Engineering degree in applied sciences from the Katholieke Universiteit Leuven, Belgium, in 2005. Currently, she is a Professor at ITU. Her main research interests include cryptography, embedded systems, and side-channel attacks.
Sr. Electrical Engineer with 40 years of experience, doing R&D, circuit design from concept through layout and to production in Aerospace, Automotive, Industrial and Gas and Oil down-hole business sectors.
30+ years industry experience in hardware and SOC design, with specialisation in Functional Verification, Silicon Validation, SI/PI and Board design
Hello, my name is Usama Ishfaq. I am an electronics engineer with expertise in IC design. With years of experience in the industry, I have developed a strong understanding of the complexities involved in designing and developing integrated circuits. My passion for electronics and technology has driven me to constantly learn and innovate, ensuring that I stay up-to-date with the latest advancements in the field. I take pride in my ability to work collaboratively with teams and clients to deliver high-quality solutions that meet their specific needs. Thank you for taking the time to read my introduction.
RTL design engineer with experience developing mobile GPUs (Samsung), high-end networking ASICs (Juniper) and CPU cores (MIPS). Co-author of lab manuals and online courses on FPGA design, RTL2GDSII flow and computer architecture. Founder of Verilog Meetup, a Silicon Valley and online community that develops open-source SystemVerilog examples targeting three niches: beginners, students who want to prepare for microarchitectural job interviews and university professors who want to avoid FPGA vendor lock (our examples are interoperable between Xilinx, Altera, Gowin and Lattice and compatible with ASIC flows, such as TinyTapeout and eFabless (in progress)).
Computer Engineering Student at the University of Notre Dame who is interested in AI and Chip Design
Senior Computer Science Student at the University of Notre Dame.
VLSI DOMAIN SKILLS --------------------------- • Digital Electronics • HDL: Verilog • HVL: System Verilog • TB Methodology: UVM • Protocols: APB, UART, I2C, SPI • EDA Tools: Modelsim, Quartus Prime, Questasim. VLSI RTL SKILLS ---------------------- • Digital Skills : Combinational and Sequential circuits • FSM • Memories • Verilog : Data types • Operators • BA and NBA • Delays in Verilog • Begin-end and fork-join Blocks • System tasks and Function • Compiler directive • FSM Coding. VLSI VERIFICATION SKILLS ------------------------------------ • System Verilog HVL: Data Types • Memories • Interface • OOPS • Constraint Randomization • Threads • Functional coverage • CRCDV • SV Testbench (Hands on SV Testbench) • Universal Verification Methodology: UVM Objects and Components • UVM Factory • UVM Phases • UVM Configuration • TLM • Virtual Sequence and Sequencer • UVM Testbench (Hands on UVM Testbench).
Seasoned VLSI professional with experience in complete chip design flow, domain experience data communication and telecom.
I am electronics engineer with 30years experience. I have very good expertise in IC packaging.
Computer Engineer at the University of Notre Dame
From Mining Gems in the field to mining data about gems and developing bleeding edge Gemological/Geological/Geophysical/Geochemical/Geospatial/Spectroscopic and other Survey, Testing, Measuring, Databasing, Retrieval, and Analytical Devices/Software/Tradecraft as well as beyond crystal unit level precision automated faceting/cutting/polishing/cabbing/carving/lapidary instruments and even 500 picometer diameter diamond polish... I do it all. Anyone in the industry wanting to spice up and drastically increase the efficiency and ROI on their wafer lapping/polishing capabilities: help me...help you...get ahead of the EUV/DUV/3nm and finer processes (my system has an RI value of less than 500pm... THAT is smaller than 8 carbon atoms in a cubic formation...carbon...not silicon...
I have recently completed a course in VLSI Design and Verification. During my training period, I have done two projects: Router Design and Verification and the second one is UART Protocol.
Senior security researcher, compiler/binary hacker, NFC ninja, hardware hacker with a FPGA hammer. Previously Pay Security.
Technical Program Manager at Efabless Corporation
Digital ASIC designer @ SenCure
Electronics Enthusiast with a passion for ML innovation
I am a recent graduate with a Major in Electronics and Telecommunication Engineering and a minor in computer engineering.
I am a highly skilled and motivated Integrated Circuit (IC) Designer with expertise in both schematic and layout design and verification. Throughout my career, I have played a key role in the development of multiple image sensor Readout Integrated Circuits (ROICs), from initial concept to final production. My key strengths include: • Schematic Design and Verification: I have extensive experience in designing and verifying top-level schematics and novel digital IP blocks for ROICs. I am proficient in using Verilog-A, PWL models, and SPICE netlists for comprehensive validation. • Layout Design and Verification: I possess a strong understanding of physical design principles and a proven track record of owning physical design for complex ROICs, including floor planning, top-level integration, and signoff. I have expertise in 3D IC integration and have developed reusable block-level layouts for various digital and analog IPs. • Design Enablement: I am passionate about creating efficient design flows. I have pioneered an open-source digital design flow and a TSV routing flow, established methodologies for 3D IC validation, and customized Calibre rules for advanced designs. I am a results-oriented individual with a keen eye for detail and a passion for innovation. I am proficient in various EDA tools and PDKs and possess excellent problem-solving and analytical skills. I am eager to contribute my expertise to a team that is developing cutting-edge imaging technologies
Design Verification Engineer with a keen sense of interest in Computer Architecture and RTL Design
Cornell Tech ECE Master of Engineering Grad '24. Interested in startups and easier access to chip design and manufacturing!
