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"profiles" search for "skills": PrimeTime

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Number of Results: 6

kartik dev pujari

i have done PGDMA in ASIC Design in physical design domain , from RV-VLSI Bangalore.

Skills

icc primetime cts sta floorplanning power analysis tcl

Area of Expertise

PNR

ardencaple

Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.

Skills

C/C++ Leadership Python Verilog VHDL DC PrimeTime

Area of Expertise

CAD: Scripting Circuits: Filters Circuits: Microcontrollers Circuits: Signal Processing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: Fabrication Process System: FPGA Programming Digital audio IoT Soc Mixed Signal

Zhiyang Ong

Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.

Skills

C/C++ Cadence Encounter Cadence NC-Verilog Cadence Virtuoso Electric CAD Electric VLSI Design System Matlab Mentor/Siemens EDA ModelSim ngspice Octave Perl Python Software Developer Synopsys Avanwaves Synopsys Cosmos Synopsys Design Compiler Synopsys HSPICE Synopsys NanoSim Synopsys PrimeTime System Verilog System-C Tcl/Tk Verilog VHDL Xilinx ISE

Area of Expertise

Academic: Research Academic: Student Analog: Design Analog: Modeling Analog: Simulation Analog: Verification CAD: Scripting CAD: Tool Development Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Signal Processing design space exploration of VLSI system designs Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Neural Networks RTL code generation SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: Test Programming VLSI layout design

Atul Agarwal

Skills

Calibre ICC2 Innovus Machine learning PrimeTime Tweaker

Area of Expertise

Digital: Placement and Routing

Kunlin Han

Skills

Cadence Virtuoso Calibre System Verilog Verilog VHDL Cadence Innovus StarRC PrimeTime

Area of Expertise

Academic: Student

Mohammed Salah

Experienced ASIC Digital Design and Physical Implementation Enthusiast

Skills

Cadence Encounter Tcl/Tk Verilog Synopsys Design compiler (DC) Synopsys Formality Synopsys ICC Synopsys ICC II Synopsys PrimeTime QuestaSim Vivado

Area of Expertise

Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis