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"profiles" search for "skills": Innovus

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Number of Results: 15

Wajeh

I have been delving into the IC design industry for the last 3 years. I started with circuit designing on Virtuoso and am now working with the APR flow for the last 1.5 year

Skills

Cadence innovus Cadence Virtuoso OpenLane

Area of Expertise

Digital: Placement and Routing

wajeh ul hasan

I have been delving into the IC design industry for the last 3 years. I started with circuit designing on Virtuoso and am now working with the APR flow for the last 1 year

Skills

cadence genus cadence innovus Cadence Virtuoso

Area of Expertise

Digital: Placement and Routing

Ethan Gao

2nd Year EECS Undergraduate student @ UC Berkeley

Skills

C/C++ Verilog Cadence Innovus

Area of Expertise

Academic: Student

Rodrigo Nogueira Wuerdig

Skills

C/C++ Cadence Virtuoso Calibre Innovus Genus

Area of Expertise

Academic: Student CAD: Scripting CAD: Tool Development Digital: Placement and Routing Digital: RTL Digital: Synthesis Miscellaneous: Cryptography System: FPGA Programming

Sajjad Ahmed

I am an graduate student of computer system engineering at Usman Institute of Technology. and working on RISCV based SoC designs since 2019 in Microelectronics Research Lab.

Skills

C C++ genus synthesis innovus digital implementation Matlab System Verilog

Area of Expertise

Academic: Research

Liban Hussein

Graduate student passionate about integrated circuit design for biomedical applications

Skills

Cadence Virtuoso Calibre Leadership System Verilog synopsys innovus

Area of Expertise

Analog: Design Analog: Layout Digital: RTL

i212437 Abdul Moiz Sheikh

Skills

C/C++ Cadence Virtuoso Verilog Cadence Innovus

Area of Expertise

Academic: Student

I have done electronic engineering from University of Engineering and Technology Peshawar in 2021, currently, i am doing MS in Electrical Engineering (Specialization in IC Design) from National University of Computer and Emerging Science(FAST-NUCES).

Skills

Cadence Genus Cadence Innovus Cadence Virtuoso Verilog

Area of Expertise

Analog: Layout Digital Synthesis Digital: Placement and Routing Digital: RTL

Jerry Yin

Skills

Cadence Virtuoso Calibre Magic CAD Verilog Cadence Innovus Synopsys Design Complier Synopsys ICC2 Synopsys Prime Time

Area of Expertise

Academic: Student VLSI Physical Design

Atul Agarwal

Skills

Calibre ICC2 Innovus Machine learning PrimeTime Tweaker

Area of Expertise

Digital: Placement and Routing

karunakar reddy kesamreddy

I am a professional in the field of Chip Design, Primary working on Synthesis, Physical Design, Static Timing Analysis and Physical Verification

Skills

Cadence Virtuoso Cadence Innovus Cadence Genus Synopsys Prime Time Synopsys IC Compiler 2 Synopsys Fusion Compiler Synopsys Design Compiler Tweaker Synopsys IC Validator Seimens Calibre

Area of Expertise

Analog: Design Digital: Synthesis Physical Design Physical Verification Static Timing Analysis

Kunlin Han

Skills

Cadence Virtuoso Calibre System Verilog Verilog VHDL Cadence Innovus StarRC PrimeTime

Area of Expertise

Academic: Student

Dhanunjaya Achari Kammari

A dedicated Physical Design Engineer aspiring to craft silicon for real-world applications.

Skills

Cadence Genus Cadence Innovus Cadence Virtuoso Calibre Python Tcl/Tk Verilog

Area of Expertise

Physical Design Scripting Synthesis

Peter Colyer

Chip Physical Design CAD Expert with 4nm Experience. Excels at unusual assignments and large scripting/programming projects. Strong debug skills. Strong Python skills. Available for full time, part time, tutoring, mentoring, consulting. ** https://www.linkedin.com/in/petercolyer ** Chip Physical Design and CAD Flow Development; Prior Roles in Reliability, Test, and ASIC Development; Software Development. • Digital Physical Implementation; • CAD Flow Script Development; • Design Rule Manual Interpretation/Application; • BS Physics Siena College, Magna Cum Laude; • BS Electrical and Computer Engineering Clarkson University, with Great Distinction; • MS Electrical Engineering Syracuse University. Based in California USA; Based in USA

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Collaboration Debugging Extraction Correllation Flow Runtime Optimization Innovus Machine Learning Perl Power Performance Area Optimization PyTest Python Root Cause Analysis SKILL Software Development STA Correlation Synopsys fusion compiler Tcl/Tk Teamwork Technology Node Install Verilog

Area of Expertise

CAD: Scripting Digital: Placement and Routing Digital: Verification PPA PPA Optimization RISC-V SoC: Floorplanning SoC: Verification SRAM System: Chip Integration