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Peter Colyer

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Email: 1petercolyer@gmail.com
Chip Physical Design CAD Expert with 4nm Experience. Excels at unusual assignments and large scripting/programming projects. Strong debug skills. Strong Python skills. Available for full time, part time, tutoring, mentoring, consulting. ** https://www.linkedin.com/in/petercolyer ** Chip Physical Design and CAD Flow Development; Prior Roles in Reliability, Test, and ASIC Development; Software Development. • Digital Physical Implementation; • CAD Flow Script Development; • Design Rule Manual Interpretation/Application; • BS Physics Siena College, Magna Cum Laude; • BS Electrical and Computer Engineering Clarkson University, with Great Distinction; • MS Electrical Engineering Syracuse University. Based in California USA; Based in USA

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Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Collaboration Debugging Extraction Correllation Flow Runtime Optimization Innovus Machine Learning Perl Power Performance Area Optimization PyTest Python Root Cause Analysis SKILL Software Development STA Correlation Synopsys fusion compiler Tcl/Tk Teamwork Technology Node Install Verilog

Area of Expertise

CAD: Scripting Digital: Placement and Routing Digital: Verification PPA PPA Optimization RISC-V SoC: Floorplanning SoC: Verification SRAM System: Chip Integration

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