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"profiles" search for "skills": System Verilog

Number of Results: 717

Karthik Mahendra

Hi! It's good to see you being here, good to believe we have same interests. Coffee Design Debug Improve OpenSource

Zeeshan Rafique

Researcher at Micro Electronics Research Lab -UIT | RISC-V Ambassador

Arsenii Terekhov

Radio Signal Processing Enthusiast

Bhawandeep Singh

Linkedin - https://www.linkedin.com/in/bhawandeep-singh-1b164517/ PhD student in CSE department in UCSC, advised by Prof. Jose Renau. My areas of majors are CPU design, digital design and embedded software.

Ahsan Ali

Passionate Electrical Engineer with interest in computer architecture and SoCs.

Klas Nordmark

Digital designer and embedded software developer. Experience from telecom and computer vision.

Julio

RTL Engineer

Area of Expertise

Digital: RTL

George Duffy

Area of Expertise

Digital: RTL

Bo Lu

Area of Expertise

Analog: Design

Federico Paredes

Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.

Martin Simlastik

digital ASIC designer with 10+ yrs experience

Paulo Roberto Bueno de Carvalho

Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.

Bob Ledzius

35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.

Santhosh

IP & SoC Verification Engineer

Jose T. de Sousa

José T. de Sousa holds a PhD degree from Imperial College London (1998) and has been a university lecturer and researcher at Lisbon University (1999-present). He holds 4 international patents, is co-author of one book, and was General Chair of the Field Programmable Logic and Applications Conference in 2013. Dr. de Sousa has published more than 70 technical papers in international journals and conferences. He was co-founder and CEO of Coreworks, a semiconductor intellectual property company, which he ran from 2001 to 2013. His specialties are digital circuit design, hardware/software architecture, technical team management and semiconductor IP marketing and sales.

CTS Chips

Electronic design house subsidiary of Cinvestav Guadalajara Unit (Center for Research and Advanced Studies), a leading research center in Mexico.

J. Rodriguez

Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.

Vishal Prafulkumar Katigar

Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)

Marco Merlin

Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.

Umer Imran

Umer Imran is eager to work in the field of Computer Architecture and Memory Consistency. He is currently working as a Design Verification Engineer at Lampro Mellon, a training firm with the vision to transform Pakistan’s talent pool into leaders of RISC-V based SoC design. He constantly aims to gain expertise in the various domains of SoC Design including IP Design, ASICs, and low power architectures.

Augustine Kuo

Vice President of Engineering - Seamless Microsystems. We design high performance AFEs using proprietary and patented technology that encodes the signal in the time-domain instead of voltage or current. This enables us to design low-power ADCs and amplifiers in scaled CMOS. Contact us if you'd like to hear more and engage our services.

Alfonso Chacon-Rodriguez

Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design. Fiction writer (National Literature Award for Novel, 2011, Costa Rica)

Komal Javed

A young and ambitious individual, eager to apply my knowledge of Computer Architecture and VLSI Physical Design to develop hardware that is performance, power and area efficient, while actively contributing to the development and growth of the open-source semi-conductor industry

MAYANK VASHISHT

Interested in Design, Verification, and Hand-off of Analog IPs. Worked on the definition, modeling, design, verification of DC-DC converters, Chargers, Ideal-Diodes, LDOs, Regulators, Bandgap references, Current limiting and sensing architectures. Excited for challenges in Analog Design, Layout and Post-silicon verification.

Eduardo Augusto da Costa

Eduardo is an Electrical Engineer engaged in hardware development with a true passion for developing and enhancing applications. While at university, he worked in a variety of projects, from VHDL in a SOC project, to a PCB for a power circuit, and even web interfaces for electronic devices network connected. He allies his technical background with great communication skills. He is used to and is passionate about working in diverse cultural environment as was his period as an international student in Japan. He also got a certification in in Digital Integrated Circuit Design and Project Flow with Cadence tools (IC Brazil Program). Currently he works at HT Micron, and is interested in positions related to chip design, hardware design, embedded software development and similar areas.

Punnu Jose Sebastian

A keen enthusiast of Si technologies

Arun Jeevaraj

ASIC Developer at Ericsson, trying hands with the open source tool flow.

Area of Expertise

Digital: RTL

Tarun Sharma

PhD Scholar at Advanced MultiCore Systems Lab, IIIT-Delhi

Daniel Limbrick

I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.

Larry Pearlstein

ASIC architect and designer. Specialize in deep learning, video, image and signal processing, and compression. Professor of Electrical and Computer Engineering at The College of New Jersey.

James Stine

Edward Joullian Endowed Chair in Engineering Oklahoma State University Department of Electrical and Computer Engineering VLSI Computer Architecture Research Group

Sang-Deok Park

I am interested in the platform-based complete SoC design/verification automation methodology and framework

Kh Shahriya Zaman

I am a PhD student at Universiti Kebagsaan Malaysia. My research interests include application-specific hardware design, mainly to accelerate machine learning applications.

Siva Prasad

Hardware Design Engineer

Jarrett Malone

Area of Expertise

Digital: RTL

Priyanka Dutta

current Phd Student in UCSC Hardware System Collective group formerly worked in Qualcomm Wireless R&D team as a design verification engineer

Luke

Student at UoC

Area of Expertise

Academic: Student

Dr. Muhammad Ali Qureshi

I am working as Associate Professor and Chairman in Department of Information & Communication Engineering, The Islamia University of Bahawalpur, Pakistan. I am also IEEE Senior Member and Chair, IEEE Bahawalpur Subsection.

2K18/EC/103 MOHD PARVEZ KHAN

myself Mohd Parvez Khan, I am pursuing btech from dtu in ECE.I have keen interest in VLSI and Digital domain.

Ravishankara K

Verification Architect

Area of Expertise

Digital: Verification

Brady Etz

Planning to enter a master's degree program in 2023. Currently employed in consumer product manufacturing. Personal project experience in embedded systems, digital verification, and RTL for FPGAs.

Kranthi Kumar Pamarthi

I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.

Brendan Ford

I am a fourth year Electrical engineering student interested in design and verification of digital and analog integrated circuits. - I have experience doing layout for RFIC using SOI processes where I gained extensive knowledge in device physics, floorplanning, ESD protection techniques, and techniques to mitigate manufacturing limitations -I have extensive experience using Cadence Virtuoso layout XL , running verification simulations using Cadence ADE Explorer, EMX, and PEX.

Rouhan Noor

I am an Electrical Engineering working VLSI design farm with 7 tape-out experiences.

Phanindra Sharma

FE Design

Area of Expertise

Digital: RTL

John Mamish

Academic researcher working at Georgia Tech

Jared Marchant

Ph.D Student studying analog/mixed-signal VLSI at Brigham Young University

Renaud GILLON

Program manager with more than 25 years experience in the semiconductor industry. Expertise in EDA tools, analogue, RF and high-voltage PDK development, sensor design, design support for electro-magnetic compatibility, ESD and functional safety.

veena S Chakravarthi

SoC Architect.Technologist. Hands-on experience in complex low power SoC designs, from concept to production. Excellent track record in successful development and production of ASICs, Technologies: Bluetooth, WLAN, IoT, Gigabit Ethernet, EPON networks, Interface ICs, Broadcast TV and Communication controllers. Demonstrated consistent track record of first-pass silicon success. PhD in Low power VLSI. Recipient of US and Indian patents. Core Competency: Chip Architecture, Micro Architecture, logic design, RTL Verilog coding, Chip level verification, Static Timing analysis, Formal Verification, design rule checking, AXI, AHB and APB bus protocols, Digital ASIC methodology, DFT methodology, Low Power ASIC design, Interfacing with backend teams, Timing closure, Post silicon bring up and validation, Project Planning, Scheduling and Management, FPGA Prototyping. Author of Book "A Practical Approach to VLSI System on Chip (SoC) Design" published by Springer Nature. Domain experience: Communications, EPON, WLAN, Bluetooth, IoT, Healthcare, Nextgen TV, Automotive. Managed dynamic, cross cultural teams of size 40 to 100. Standards worked on IEEE802.3, IEEE802.11b, ac, ad. ATSE 3.0, Automotive ethernet, Bluetooth Quality standards: ISO 9002, ISO 13485, IEC 60601-2 Funded Research: Derivative Low power standard cell library development PhD Guidance: 2 one in Asynchronous VLSI design methodology and second in Sub 1V power supply for complex SoCs. Co-founded healthcare company:Sensesemi Technologies Pvt. Ltd. Academic research head and taught engineering students for their undergrad, Post grad and PhD courses Chair, IEEE NanoTechnology Council, Bangalore Section as a founder Chairperson, Current Senior IEEE member.

Marc C.

Area of Expertise

Digital: RTL

Chaganati Harsha Vardhan Reddy

I'm Harsha, pursuing my under graduation in the stream of Electronics and Communication Engineering at SRM University AP

Rohit Khanna

Hardware Design Engineer with 7 years of experience in RTL/SoC/FPGA Design, Integration, and Verification. Proficient in Front End Design tools and methodologies. Passionate about IC Design/Fabrication, AI, and IoT prototyping.

Shabbar Vejlani

Digital and Mixed Signal Verification Engineer, with 9+ years of industry experience, looking to explore the entire chip design cycle.

Zong-Ru Li

2nd year MS student in ECE, looking for joining an ASIC project.