Hi! It's good to see you being here, good to believe we have same interests. Coffee Design Debug Improve OpenSource
im a student who want learn design VHDL
Silicon Design Engineer
Linkedin - https://www.linkedin.com/in/bhawandeep-singh-1b164517/ PhD student in CSE department in UCSC, advised by Prof. Jose Renau. My areas of majors are CPU design, digital design and embedded software.
Digital designer and embedded software developer. Experience from telecom and computer vision.
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
I am Electronic Engineer from Chile, I like DSP and radioastronomy applications an ordinary guy
Analog Mixed Signal IC Designer
Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.
Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.
Learner for life
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
Teaching assistant for ASIC/FPGA and digital ICs courses.
José T. de Sousa holds a PhD degree from Imperial College London (1998) and has been a university lecturer and researcher at Lisbon University (1999-present). He holds 4 international patents, is co-author of one book, and was General Chair of the Field Programmable Logic and Applications Conference in 2013. Dr. de Sousa has published more than 70 technical papers in international journals and conferences. He was co-founder and CEO of Coreworks, a semiconductor intellectual property company, which he ran from 2001 to 2013. His specialties are digital circuit design, hardware/software architecture, technical team management and semiconductor IP marketing and sales.
Electronic design house subsidiary of Cinvestav Guadalajara Unit (Center for Research and Advanced Studies), a leading research center in Mexico.
Lecturer UiTM
Physical Design Engineer
Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.
Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)
Physical design engineer
Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.
Umer Imran is eager to work in the field of Computer Architecture and Memory Consistency. He is currently working as a Design Verification Engineer at Lampro Mellon, a training firm with the vision to transform Pakistan’s talent pool into leaders of RISC-V based SoC design. He constantly aims to gain expertise in the various domains of SoC Design including IP Design, ASICs, and low power architectures.
Vice President of Engineering - Seamless Microsystems. We design high performance AFEs using proprietary and patented technology that encodes the signal in the time-domain instead of voltage or current. This enables us to design low-power ADCs and amplifiers in scaled CMOS. Contact us if you'd like to hear more and engage our services.
Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design. Fiction writer (National Literature Award for Novel, 2011, Costa Rica)
A young and ambitious individual, eager to apply my knowledge of Computer Architecture and VLSI Physical Design to develop hardware that is performance, power and area efficient, while actively contributing to the development and growth of the open-source semi-conductor industry
Managing Partner
Interested in Design, Verification, and Hand-off of Analog IPs. Worked on the definition, modeling, design, verification of DC-DC converters, Chargers, Ideal-Diodes, LDOs, Regulators, Bandgap references, Current limiting and sensing architectures. Excited for challenges in Analog Design, Layout and Post-silicon verification.
Physical Design Engineer
Eduardo is an Electrical Engineer engaged in hardware development with a true passion for developing and enhancing applications. While at university, he worked in a variety of projects, from VHDL in a SOC project, to a PCB for a power circuit, and even web interfaces for electronic devices network connected. He allies his technical background with great communication skills. He is used to and is passionate about working in diverse cultural environment as was his period as an international student in Japan. He also got a certification in in Digital Integrated Circuit Design and Project Flow with Cadence tools (IC Brazil Program). Currently he works at HT Micron, and is interested in positions related to chip design, hardware design, embedded software development and similar areas.
ASIC Developer at Ericsson, trying hands with the open source tool flow.
PhD Scholar at Advanced MultiCore Systems Lab, IIIT-Delhi
I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.
ASIC architect and designer. Specialize in deep learning, video, image and signal processing, and compression. Professor of Electrical and Computer Engineering at The College of New Jersey.
Edward Joullian Endowed Chair in Engineering Oklahoma State University Department of Electrical and Computer Engineering VLSI Computer Architecture Research Group
Assistant Professor (IISc) | Ph.D. & S.M. (MIT) | B.Tech. (IIT-KGP)
I am interested in the platform-based complete SoC design/verification automation methodology and framework
I am a PhD student at Universiti Kebagsaan Malaysia. My research interests include application-specific hardware design, mainly to accelerate machine learning applications.
current Phd Student in UCSC Hardware System Collective group formerly worked in Qualcomm Wireless R&D team as a design verification engineer
Principal engineer leading PNT product development at GE Aerospace
I am working as Associate Professor and Chairman in Department of Information & Communication Engineering, The Islamia University of Bahawalpur, Pakistan. I am also IEEE Senior Member and Chair, IEEE Bahawalpur Subsection.
A researcher and VLSI guy
myself Mohd Parvez Khan, I am pursuing btech from dtu in ECE.I have keen interest in VLSI and Digital domain.
Doctoral student at the Tokyo Institute of Technology.
Planning to enter a master's degree program in 2023. Currently employed in consumer product manufacturing. Personal project experience in embedded systems, digital verification, and RTL for FPGAs.
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
Experienced SW developer (C/C++/C#) and digital HW designer (SoC/FPGA)
I am a fourth year Electrical engineering student interested in design and verification of digital and analog integrated circuits. - I have experience doing layout for RFIC using SOI processes where I gained extensive knowledge in device physics, floorplanning, ESD protection techniques, and techniques to mitigate manufacturing limitations -I have extensive experience using Cadence Virtuoso layout XL , running verification simulations using Cadence ADE Explorer, EMX, and PEX.
I am an Electrical Engineering working VLSI design farm with 7 tape-out experiences.
PhD student working on a superconducting FPGA design aiming to work on neuromorphic computing in the future.
Ph.D Student studying analog/mixed-signal VLSI at Brigham Young University
Program manager with more than 25 years experience in the semiconductor industry. Expertise in EDA tools, analogue, RF and high-voltage PDK development, sensor design, design support for electro-magnetic compatibility, ESD and functional safety.
SoC Architect.Technologist. Hands-on experience in complex low power SoC designs, from concept to production. Excellent track record in successful development and production of ASICs, Technologies: Bluetooth, WLAN, IoT, Gigabit Ethernet, EPON networks, Interface ICs, Broadcast TV and Communication controllers. Demonstrated consistent track record of first-pass silicon success. PhD in Low power VLSI. Recipient of US and Indian patents. Core Competency: Chip Architecture, Micro Architecture, logic design, RTL Verilog coding, Chip level verification, Static Timing analysis, Formal Verification, design rule checking, AXI, AHB and APB bus protocols, Digital ASIC methodology, DFT methodology, Low Power ASIC design, Interfacing with backend teams, Timing closure, Post silicon bring up and validation, Project Planning, Scheduling and Management, FPGA Prototyping. Author of Book "A Practical Approach to VLSI System on Chip (SoC) Design" published by Springer Nature. Domain experience: Communications, EPON, WLAN, Bluetooth, IoT, Healthcare, Nextgen TV, Automotive. Managed dynamic, cross cultural teams of size 40 to 100. Standards worked on IEEE802.3, IEEE802.11b, ac, ad. ATSE 3.0, Automotive ethernet, Bluetooth Quality standards: ISO 9002, ISO 13485, IEC 60601-2 Funded Research: Derivative Low power standard cell library development PhD Guidance: 2 one in Asynchronous VLSI design methodology and second in Sub 1V power supply for complex SoCs. Co-founded healthcare company:Sensesemi Technologies Pvt. Ltd. Academic research head and taught engineering students for their undergrad, Post grad and PhD courses Chair, IEEE NanoTechnology Council, Bangalore Section as a founder Chairperson, Current Senior IEEE member.
I am professor at Dept of EEE, BUET, Passionate to teach students IC Design and Fabrication Skill.
I'm Harsha, pursuing my under graduation in the stream of Electronics and Communication Engineering at SRM University AP
Hardware Design Engineer with 7 years of experience in RTL/SoC/FPGA Design, Integration, and Verification. Proficient in Front End Design tools and methodologies. Passionate about IC Design/Fabrication, AI, and IoT prototyping.
Digital and Mixed Signal Verification Engineer, with 9+ years of industry experience, looking to explore the entire chip design cycle.
Experienced Senior Design Engineer with a demonstrated history of working in the electrical and electronic manufacturing industry. Skilled in DAC, SPICE, ADCs, Electronics Hardware Design, and Management. Strong engineering professional with a M-Tech focused in VLSI System Designs from Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering &Technology and also a B-Tech Degree in the field of Electrical, Electronics and Communications Engineering from Mahatma Gandhi Institute of Technology.
I am working at Object Automation
I am Anuj Kumar Jha and pursuing MTech at IIIT Bangalore in VLSI
I`m a digital IC designer working for a RISC-V company RIVAI in China, which has close ties with RIOS Lab.
I am a Senior Undergraduate in Electrical Engineering Department at IIT Gandhinagar, India. VLSI Design and the ability to tweak at the hardware level interest me a lot!
Cryptography and security researcher at Seagate Technology
VLSI Professional with 2.3 years of experience and adequate knowledge in RTL Design, UPF, SDC, Lint, CDC, Synthesis, Physical Design, STA and Scripting. I love Computers and I am interested in RISC V
I am a Graduate student pursuing my master's in Computer Engineering. I am interested in VLSI projects.
RF/Analog IC design and SOC
ASIC and FPGA design and verification Engineer with a sideline in bring devops to Hardware projects
Currently a student in EE, interested in ASIC design and logic synthesis
William Oswald received the B.S. degree in computer engineering and the M.S. degree in electrical engineering from the University of South Alabama, in 2020 and 2021, respectively. He is currently pursuing the Ph.D. degree in systems engineering. He has worked in industry as a Systems Analyst at Packaging Corporation of America, from 2019 to 2020. His research interests include computer architecture design, machine learning, and model based systems engineering.
Just another big dreaming engineer with a desire to learn silicon microfab
Received B.S. degree from Electrical and Electronics Engineering in Middle East Technical University, Turkey, in 2019. Currently, pursuing M.S. degree from Electronics Engineering in Bogazici University, Turkey. Research interests are computer architecture, hardware security and secure memory architecture
13+yr ASIC Digital Designer. Master degree on Microeletronic Sensors. Worked on NXP through different projects on automotive and consumer/general market MCUs on areas from SoC Integration to Timing Sign-Off
Digital System Designer.
I am an graduate student of computer system engineering at Usman Institute of Technology. and working on RISCV based SoC designs since 2019 in Microelectronics Research Lab.
I am a student at IIIT Bangalore pursuing Integrated Mtech in Electronica and Communications Engineering and am fascinated about silicon wafers and want to pursue a career and build a revolution in this domain.
Final year student of Electrical Engineering at UET Lahore. Area of expertise is Digital Design, Computer Architecture and SOCs.
ASIC Verification Engineer with 12+ yrs of exp.
Electrical Engineering student at UFMG, scheduled to graduate in Dec/2022. Experience in the automotive sector by the Formula Tesla UFMG team, designing electrical and electronic systems. Exchange experience in South Africa for 3 months studying English and working voluntarily in needy settlements. Currently, work as Software Engineer at Cadence Design Systems.
Hon-Piu Lam, is a Ph.D. candidate in the Department of Electronic and Computer Engineering of the Hong Kong University of Science and Technology (HKUST). He was an analog IC designer engineer in Valence Semiconductor from 2004 to 2007. From 2007 to 2015, he joined Fujitsu Semiconductor focusing on the embedded NOR flash design. He has been a researcher in HKUST focusing on the integrated power electronic and data converter. His research interests include readout electronics, integrated power electronics and radiation hardened electronics for experimental physics.
I am a student who is currently taking a deep dive into the world of ASICs.
Graduate student passionate about integrated circuit design for biomedical applications
I am en Electronics Engineer currently Pursuing my Masters in IC design from FAST NUCES Islamabad.
Post-doctoral research fellow in the discipline of Software and Systems, School of Computer Science and Statistics, Trinity College Dublin, with a keen interest in learning new things, specially related to computer science and engineering. Around 4 years experience of teaching and research and more than 10 years of experience in architecture design, optimization, analysis, implementation and verification of digital and digital signal processing systems on FPGAs and ASICs. Diversifying research career by working on quantization of deep convolution neural networks. Author of three peer reviewed journal publications and five international conference publications.
electronic system designer / software and hardware engineer, embeded system expert, signal expert, proccess designer, researcher, Developer of complexity and reversal wantings. Reverse engineer. i addopt my whole life to this science. thank you for presentings of quantum, psych
Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.
I'm a new grad Digital Design engineer working. Looking forward to contribute to open source silicon projects.
Independent Digital Design and Verification Expert with more than 20+ years of experience and founder of semify. While working for established semiconductor companies like Infineon, Dialog Semiconductor and NXP I was responsible for bringing ideas into working ASICs. I developed USound’s first ASIC from FPGA based prototyping to tapeout with minimal resourcing, demanding timeline and tight area and power consumption constraints. Currently I'm acting as a consultant for easyIC and Cypress / Infineon. In addition I'm is also lecturer at the FH Joanneum Graz and guest lecturer at the Technical University Graz.
Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.
hello, my name is Darshan Guled, i am an engineering student and i am working on PICO RISc processor and RAVEN chip,
U.G. Student at IIT Gandhinagar.
I am a student pursuing my masters in the field of VLSI
currently doing mtech in vlsi domain,want to gain knowledge in physical design and asic design flow
A digital design engineer, interested in memory hierarchies and high speed interfaces.
Hello I am Rakesh , I am pursuing my Under Graduation in Electronics and Communication Engineering at KLE Technological University, Hubballi. I am looking ahead work in Digital VLSI Domain. :D
Hello I'm sultan, and I'm from KLE technological University hubli and I'm very exited to do this course on picorisc.
RISC-V Enthusiast GSoC 2020 @ FOSSi Foundation RA @ CAD Lab, IISc Bengaluru, India EE Senior @ NITK Mangalore, India
I’m an engineer always looking to learn, optimize and automate. I work on data analytics to provide deep insights into hardware designs, particularly physical design flow. Exploring areas to facilitate design engineers in taking data driven decisions for faster design turnaround times. I like to think about life. I like experimenting with different techniques (using software tools and meditation) to optimize my day and work effectively. In my free time, I’m learning Web Programming to build my own blog. I know there are templates and websites but where’s the fun and learning if you don’t do it from scratch? I like mentoring students on how to approach career and life in general.
President and CEO
R&D Engineer
Verification engineer and quick learner and really enthusiastic to learn new things
IP, SOC RTL Design engineer, Microarchitecture. Knowledge of Front End
Dad. Partner. Scientist. Activist. Maker. — He/His
SubIP and SoC Design Verification Engineer. Extends to running Full Chip Emulation on Palladium and Protium Platforms.
Research Associate at Micro Electronics Research Lab (MERL) working as a hardware design engineer.
I'm a PhD student working to make mixed-signal chip design more accessible, drawing inspiration from software development techniques. Prior to starting the PhD program, I spent a number of years working in industry at both the chip- and PCB-level on optical sensors and power systems.
Dr Tapas Kumar Maiti, a former associate professor at Hiroshima University Japan, moved to DA-IICT India where he is a faculty member, since June 2019. He was a visiting faculty to IIEST-Shibpur. He has amazing research experience at McMaster University, Canada and IIT-Kharagpur. He has published more than 100 papers in reputed journals and conferences, and also co-authored a book. He received ICMM Excellent Presentation Award, IAAM Scientist Medal, and University Gold Medal. He is a member of IEEE, and Life Member of IEI. Currently, he is working in the areas of Intelligent Computing Devices, Robotics, and Cybernetics.
Hello everybody! I am a FPGA developer in Croatia, I do FPGA project and am starting ASIC design as another careere choice.
I am currently working as a Research Associate. We are doing research and development on RISC-V Technology.
Ali Ahmed is an Assistant Professor of Electrical Engineering at UiT, Karachi. His current broader research interests are in computer architecture, IoT, and Information Security. He is especially interested in micro-architecture, with a major current focus on memory and storage systems. He has 10+ year experience in complete Product development Cycle of CoTs (hardware and software). Involved in product development from scratch, hardware designing, middle ware and application level development. Well versed in hardware platforms like FPGA s and Microcontrollers. He obtained his PhD and MS in ECE from the Hanyang University, South Korea where he designed and Implemented memory architecture of SRAM-based Ternary Content Addressable Memory using Xilinx Kintex-7 FPGA ( http://ieeexplore.ieee.org/document/7797247/) He obtained BE degrees in Electronics Engineering from the NED university of Engineering and Technology, Karachi. His industrial experience spans starting the Product development division at Horizon Tech, Islamabad (2008-2012).
My name is Joel Sanchez Moreno I graduated as a Computer engineer and I currently work as a full time RTL design engineer for a start up. In addition, I am doing a part-time master on High Performance Computing on the Universitat Politècnica de Catalunya (UPC)
Hi, I'm an Electrical & Computer Engineering + Computer Science student at Oregon State University.
Dynamic and career-oriented VLSI Verification Trainee. Looking for a responsible position as a VLSI verification engineer with a view to utilize and enhance my skills and experience towards professional and personal growth.
Digital Systems and Software Engineer (formerly in management VP and Director of engineering).
Research Associate at MERL mainly focusing of firmware and driver development for SoCs.
I am a final year B.Tech undergrad from India highly passionate about digital system design.
I am accomplished digital design engineer having 8 years of industrial expertise . I am currently working on IP design and IP integrations stuffs .
Electrical Engineer, pursuing a Masters in Microelectronics
A bit of everything - mostly focused on networking system level designs / FPGA / Switch Fabric from concept to validation - and now automotive
Osaze Shears is passionate about many engineering and computational concepts. These include embedded systems, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and microprocessor technologies. Osaze spends his free time tutoring other students who are interested in learning to become better computer scientists and engineers to benefit the greater society. Osaze is currently a PhD student at Virginia Tech conducting research under the Multifunctional Integrated Circuits and Systems (MICS) lab. His research interests include: • Spiking Neural Networks • Hardware Acceleration • SoC Design with ASICs and FPGAs • Deep Learning • Edge Computing
Microelectronics Enthusiastic, Vast experience in embedded design for various domains.
ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.
I am an enthusiastic proponent of open source hardware. See my position paper on the topic: https://ieeexplore.ieee.org/document/7945172.
I am a young student, growing high with a passion for VLSI. I am highly interested in working on high-speed low-power RTL chip design.
Designer specialized on VLSI radiation tolerant architectures and circuits
I am currently a postgraduate student at the University of Calcutta and graduate with a Bachelor of Science Degree in Electronics, which will broaden my aptitude in numerous aspects. The curriculum is designed for proficiency in problem-solving techniques, organizational skills, and other mechanics that will help me to execute solutions. Which gives me the opportunity to explore in-depth learning experiences in various technology. I am interested in astrophysics, radio astronomy, solar physics, and other space and atmospheric research, also in semiconductor physics and VlSI technology.
I'm currently a PhD candidate at Stanford studying Electrical Engineering with Prof. Priyanka Raina. I graduated from Princeton with high honors in Electrical Engineering and certificates in Applications of Computing and Engineering Physics. I completed my Stanford M.S. degree in EE; my current PhD research focuses on emerging memory/circuit technologies (resistive RAM/NEM relays) and efficient reconfigurable computing (FPGAs/CGRAs). I consider myself an eclectic learner who has never been satisfied to work in just a single area. In the past, I've done research projects across an extremely wide array of subjects, including oxide nanoelectronics (Prof. Patrick Irvin, Pitt), stochastic simulation of biochemical processes (Prof. Marcus Dittrich, PSC), deep learning applied to petroleum well data (Prof. Verena Kaynig-Fittkau, Harvard/QRI), and development of quantum cascade devices in group-IV materials (Prof. Claire Gmachl, Princeton). My senior thesis at Princeton with Prof. Prateek Mittal was focused on privacy threats posed by Content Delivery Networks. I've also worked as a software intern at two companies, GoFundMe and Amazon; there, I took on data science and analytics problems affecting business. Recently, I completed an (entirely virtual!) internship at NVIDIA focused on improving circuit design with AI. Additionally, I have several personal projects I'm proud of: an analytics engine for online Set! to understand how people learn the card game, enabling Amazon Alexa home assistants to rap battle each other, studying graph techniques for understanding musical collaborations... and so on. I love meeting/hearing ideas from new people, so feel free to contact me. Cheers!
Hi I'm a MASc Student at University of Toronto. My research focuses are FPGA architecture, DL Acceleration, Heterogenous devices and CAD tools.
My name is Sunil Parmar, I have done a master from IIT-Bombay in 2005 and a bachelors from Gujarat University in 2003. After post-graduation, I joined a service company in Hyderabad and later worked with Intel Bangalore. I have worked with the Samsung R&D center in South Korea for Silicon photonics applications and later contributed in Samsung's DDR4 memory IO design. As an employee, I have published few patents and papers. In 2016, I returned to India with a very ambitious goal to set up a semiconductor product company called Powency Circuit Private Limited in the power management domain. In between, After Covid, I decided to develop a MEMS Microphone product and started a project called Sikern. We are currently a small team having three design engineers, one packaging expert and one management staff. We are working with a Japanese supplier and a Malaysian packaging group for our product development. And developing our own ASIC for this MEMS microphone. We started working with a smartphone customer in India for their upcoming mobile model. And hope to work with many more customers within India as well across the globe for our Microphone product.
Hardware System Designer from ASIC chip to board to SOC platform
I am a senior ASIC and IP development person. My strength is in building high performance ASIC teams that deliver high quality ASIC and IP products .
I'm the founder of reconfigurable computing. https://bit.ly/WhoIsSteveCasselman
"Architecting the dreams of a digital future, pixel by pixel, gate by gate."
Retired engineer interested in SV and SVA. Wrote several books and papers on SVA, PSL, VMM, chip design and verification, VHDL. Ben@systemverilog.us Link to the list of papers and books that I wrote, many are now donated. http://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf or https://rb.gy/ibks5p
Researcher at Indian Institute of Technology, Bombay
I'm a Graduate Research and Teaching Assistant at Oregon State University.
Cal Poly CARP is a computer architecture research group of professors and students at Cal Poly, San Luis Obispo, that has the goal of developing a framework for building SoCs. The advising professor is Joseph Callenes-Sloan.
I'm a PhD student focusing on the Edge AI accelerators and Neuromorphic computing at Edge AI Acceleration Lab, Singapore University of Technology and Design
Graduate student in MIT EECS trying to combine stochastic MTJ devices to silicon
I majored in electronic science and technology for my undergraduate degree and integrated circuit engineering for my postgraduate degree. During this period, my research direction was analog integrated circuit design and application.
i am a vlsi enthusiast
Passionate about digital electronics and aspiring to launch a career in this dynamic field. Currently seeking an internship opportunity to apply and further develop my knowledge and skills in digital electronics design, verification, circuit analysis, and FPGA programming. Implemented CORDIC Algorithm, UART Tx and Rx module and the Baud rate Generator, Single cycle Risc-v 32 bit processor and LFSR(Linear feedback shift register) , all using Verilog HDL. I am enthusiastic about learning from industry professionals and contributing to innovative projects. With a solid foundation in Verilog HDL, digital logic and a strong drive for continuous growth, Open to opportunities that foster professional development and hands-on experience in digital electronics.
PRODUCTS AND CONSULTING IN AEROSPACE, SEMICONDUCTORS, SAAS, ROBOTIC EQUIPMENTS, COMPUTE SYSTEMS, QUANTUM, TELECOM AND INDUSTRIAL.
An aspiring young electrical engineering student from Pakistan trying to learn and build my expertise in the FPGA/SoC development world with Xilinx Zynq platforms. Working on a machine learning accelerator on Digilent Cora Z7 (Zynq 7000 series SoC) board for my senior year project.
Berna Örs Yalçın received the Electronics & Communication Engineering degree and the MSc degree in 1995 and 1998, respectively, both from the Istanbul Technical University (ITU), Turkey. She received the Electrical Engineering degree in applied sciences from the Katholieke Universiteit Leuven, Belgium, in 2005. Currently, she is a Professor at ITU. Her main research interests include cryptography, embedded systems, and side-channel attacks.
Simple and understanding
A recent Electronic Engineering graduate
30+ years industry experience in hardware and SOC design, with specialisation in Functional Verification, Silicon Validation, SI/PI and Board design
Junior (3rd Year) Electrical Engineering Undergraduate at the University of Notre Dame and Cornell SUPREME Microelectronics Fellow Previous work experience includes an extensive research background in nanomaterial synthesis and novel semiconductor-based memory devices, and coursework in digital integrated circuit design. Includes over 350 hours of cleanroom experience and proficiency with various analytical and scientific instrumentation and software. Published 1 first-author IEEE conference paper. Co-authored a conference paper accepted to IEDM 2024 and one journal paper submitted to ACS Nano. Club experience includes holding an officer position (Secretary) and Electrical Team Lead in the Robotic Football Club (RFC), with a focus on robotics and hardware engineering. Plays the Tuba with the University of Notre Dame Band of the Fighting Irish at various sporting events and other performances. Holds 4X consecutive Dean's List standings and membership in IEEE HKN and TBP, demonstrating consistent academic excellence.
RTL design engineer with experience developing mobile GPUs (Samsung), high-end networking ASICs (Juniper) and CPU cores (MIPS). Co-author of lab manuals and online courses on FPGA design, RTL2GDSII flow and computer architecture. Founder of Verilog Meetup, a Silicon Valley and online community that develops open-source SystemVerilog examples targeting three niches: beginners, students who want to prepare for microarchitectural job interviews and university professors who want to avoid FPGA vendor lock (our examples are interoperable between Xilinx, Altera, Gowin and Lattice and compatible with ASIC flows, such as TinyTapeout and eFabless (in progress)).
FPGA/HW engineer
Product design and development
VLSI DOMAIN SKILLS --------------------------- • Digital Electronics • HDL: Verilog • HVL: System Verilog • TB Methodology: UVM • Protocols: APB, UART, I2C, SPI • EDA Tools: Modelsim, Quartus Prime, Questasim. VLSI RTL SKILLS ---------------------- • Digital Skills : Combinational and Sequential circuits • FSM • Memories • Verilog : Data types • Operators • BA and NBA • Delays in Verilog • Begin-end and fork-join Blocks • System tasks and Function • Compiler directive • FSM Coding. VLSI VERIFICATION SKILLS ------------------------------------ • System Verilog HVL: Data Types • Memories • Interface • OOPS • Constraint Randomization • Threads • Functional coverage • CRCDV • SV Testbench (Hands on SV Testbench) • Universal Verification Methodology: UVM Objects and Components • UVM Factory • UVM Phases • UVM Configuration • TLM • Virtual Sequence and Sequencer • UVM Testbench (Hands on UVM Testbench).
Dedicated, innovative and enthusiastic individual with consolidated expertise in Digital Electronics, Data Sciences, Robotics and IoT. A confident leader who effectively collaborates with the team members to accomplish all goals in an accurate and timely manner.
I am ASIC digital designer engineer, always keen to explore new alternatives, methodologies, designs. I like challenges and always proactive to help.
Based in India, developing a new SoC type.
A PhD student working in WEST (Wireless Environmental Sensor Technology) Lab with a focus on Analog IC design.
Computer Engineering Student at the University of Notre Dame
I am currently in my junior year studying computer engineering at the University of Notre Dame. Alongside that, I am pursuing a concentration in cybersecurity and a minor in engineering corporate practice. My curiosity was initially drawn to the puzzle-like nature of security problems, which led me to major in Computer Engineering in an effort to dissect both the hardware and software sides of computer systems and expose their vulnerabilities. The more I learned about cybersecurity, the more I realized its criticality in safeguarding individuals and organizations and its ever-growing prominence in our tech-driven world, especially within software development. Throughout my undergraduate career, I have taken on various leadership positions, from acting as the Vice President of my university's Engineers Without Borders chapter to leading development teams at CS For Good. I expect to graduate in May 2025, and I am currently interested in an internship position for the summer of 2024.
CSE Professor at the University of Notre Dame
I am currently in my junior year studying computer engineering at the University of Notre Dame. Alongside that, I am pursuing a concentration in cybersecurity and a minor in engineering corporate practice. My curiosity was initially drawn to the puzzle-like nature of security problems, which led me to major in Computer Engineering in an effort to dissect both the hardware and software sides of computer systems and expose their vulnerabilities. The more I learned about cybersecurity, the more I realized its criticality in safeguarding individuals and organizations and its ever-growing prominence in our tech-driven world, especially within software development. Software engineering complements that passion but adds a layer of creativity and ingenuity that fuels my drive to develop programs and systems that help serve people all over the world. I strive to build solutions that are not only resource-efficient but also sustainable, scalable, and adaptable. Achieving this goal requires a relentless passion for learning about available and emerging technologies – a skill I am proud to have. I am fascinated by the ever-evolving landscape of tech innovation, and it is this fascination that motivates me to delve deeper into the world of technology, continuously seeking out new knowledge and skills to ensure I stay at the forefront of this dynamic industry. Throughout my undergraduate career, I have taken on various leadership positions, from acting as the Vice President of my university's Engineers Without Borders chapter to leading development teams at CS For Good. I expect to graduate in May 2025, and I am currently interested in an internship position for the summer of 2024.
I am a Computer Engineer at the University of Notre Dame, with minors in Innovation and Entrepreneurship and Corporate Engineering Practices. I enjoy working with assembly languages and at the circuit level.
I am electronics engineer with 30years experience. I have very good expertise in IC packaging.
ASIC Designer with experience in Back-end & Front-end stages for ASIC design flow.
Electrical Engineer with five years of expertise in FPGA Design and Embedded Systems, cultivated through roles at prestigious organizations like RapidSilicon, Pakistan Air Force, and NRTC. Proficient in RTL design, verification, and protocol implementation. Experienced in scripting, simulation tools, and FPGA technologies. Seeking dynamic career opportunities to further enhance complex digital design systems and contribute to semiconductor innovation.
Fresh Electronics and Computer Engineering graduate from Nile University with magna cum laude distinction. Interested in computer architecture design using AI. Have an experience with digital IC design, data analysis, machine learning, software engineering, and system administration. Currently, working at the NISC research center in Nile University as a part-time research assistant in the field of microarchitecture design.
From Mining Gems in the field to mining data about gems and developing bleeding edge Gemological/Geological/Geophysical/Geochemical/Geospatial/Spectroscopic and other Survey, Testing, Measuring, Databasing, Retrieval, and Analytical Devices/Software/Tradecraft as well as beyond crystal unit level precision automated faceting/cutting/polishing/cabbing/carving/lapidary instruments and even 500 picometer diameter diamond polish... I do it all. Anyone in the industry wanting to spice up and drastically increase the efficiency and ROI on their wafer lapping/polishing capabilities: help me...help you...get ahead of the EUV/DUV/3nm and finer processes (my system has an RI value of less than 500pm... THAT is smaller than 8 carbon atoms in a cubic formation...carbon...not silicon...
I have recently completed a course in VLSI Design and Verification. During my training period, I have done two projects: Router Design and Verification and the second one is UART Protocol.
Embedded Software designer
Hao-Yen Tang received his PhD degree from UC Berkeley Advised by Prof. Bernhard E. Boser, his PhD research, PMUT ultrasonic fingerprint sensor, convince InvenSense senior management to make a heavy investment to take this technology to mass market. At InvenSense he’s leading a multi-disciplinary system team for the next generation ultrasonic fingerprint sensor bringup, characterization and calibration, coordinating the works from different field including acoustic, MEMS, CMOS, FW, and SW. Currently, he serves as CTO/Co-Founder in the startup company UltraSense Systems. The company is aiming to transform any surface material into a Touch/Press user interface with it’s proprietary PiezoMEMS-CMOS technology. Dr. Tang is the recipient of 2016 ISSCC Best Paper Award (Lewis Winner Award for Outstanding Paper), 2015 SSCS Pre-Doctoral Award and 2015 ADI Outstanding Student Designer Award. Currently he holds 20+ granted patents, 20+ publications, and 2000+ citations.
We are an undergraduate chip design team at Cornell University dedicated to open-source design!
Senior security researcher, compiler/binary hacker, NFC ninja, hardware hacker with a FPGA hammer. Previously Pay Security.
Software developer / electronics enthusiast
College Student into VSLI and digital design realted things
Director - RTL Mfra Tech
Digital ASIC designer @ SenCure
I am a professor in computer engineering at the Faculty of Computer and Information Science, University of Ljubljana, Slovenia. My research interests include computer architecture and organization, parallel processing, computer arithmetic, embedded systems, and VLSI design.
Electronics Enthusiast with a passion for ML innovation
I am a recent graduate with a Major in Electronics and Telecommunication Engineering and a minor in computer engineering.
Electronics and Communication Graduate from Vidyavardhaka College of engineering.
Design Verification Engineer with a keen sense of interest in Computer Architecture and RTL Design
An undergraduate Electrical Engineering student from Pakistan passionate about chip design, aspiring to dive into Silicon Valley's cutting-edge chip innovation. With a robust foundation in embedded systems and proficiency in C, C++, Python, CSS, and Java, they aim to excel in the tech industry, blending their technical expertise with a flair for creative article writing. As a dedicated IEEE member and certified volunteer administrator, they have a vision to shape the future of technology through innovation and exploration.
Student of Electrical & Computer Engineering. Technology lover :)
I am currently a Design Verification Intern and I am looking to bolster my thought processes more in this world of RTL Design and Computer Architecture
Cornell Tech ECE Master of Engineering Grad '24. Interested in startups and easier access to chip design and manufacturing!
As a VLSI enthusiast, I completed a 6-month internship as a NAND product engineer at Micron Technology where my work comprises of post-silicon validation, data analysis using JMP, and testing NAND components under varying PVT conditions in DDR3 and LPDDR4. I'm passionate about CMOS and have experience simulating NAND output drivers through HSPICE simulations in collaboration with the design team. Additionally, I have proficiency in System Verilog, RTL design, and a solid grasp of digital IC, analog IC, and physical design. I hold a master's degree in Microelectronics from BITS Hyderabad and a bachelor's degree in ECE from Gayatri Vidya Parishad. I achieved a GATE ECE score of 571 with an All India Rank (AIR) of 1404 in 2023. devadeepreddi20@gmail.com
Greetings! I, Devang Sharma am a B.Tech final year student studying at Jaypee Institute, Noida. I am a VLSI-enthusiast and posses moderate to advanced-level skillset(at B.Tech level). I have studied about ASIC Design Flow and learnt several HDLs(Verilog, SV, UVM).
computer architect, chip design verfication engineer.
