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"profiles" search for "skills": Universal verification methodology
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Number of Results: 2

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Jayesh parmar

ASIC verification engineer

Skills

System Verilog Verilog Universal verification methodology

Area of Expertise

Digital: Verification
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Pallavi Kar

I have recently completed a course in VLSI Design and Verification. During my training period, I have done two projects: Router Design and Verification and the second one is UART Protocol.

Skills

System Verilog Verilog Universal Verification Methodology Digital Electronics Linux

Area of Expertise

Academic: Student Digital: RTL Digital: Verification