Efabless Logo

Tag Search

"profiles" search for "skills": Universal Verification Methodology
Open Search

Number of Results: 2

entry image

Jayesh parmar

ASIC verification engineer

Skills

System Verilog Verilog Universal verification methodology

Area of Expertise

Digital: Verification
entry image

Pallavi Kar

I have recently completed a course in VLSI Design and Verification. During my training period, I have done two projects: Router Design and Verification and the second one is UART Protocol.

Skills

System Verilog Verilog Universal Verification Methodology Digital Electronics Linux

Area of Expertise

Academic: Student Digital: RTL Digital: Verification