Analog IC Design Engineer with considerable expertise in mid- to high-frequency transistor-level design in the semiconductor industry, including clock synthesis, radio frequency circuitry (RF), and memory circuitry design. Experience also includes testing at board- and wafer-level, test automation, and simulation scripting.
Linkedin - https://www.linkedin.com/in/bhawandeep-singh-1b164517/ PhD student in CSE department in UCSC, advised by Prof. Jose Renau. My areas of majors are CPU design, digital design and embedded software.
I am a software developer, trying to learn about hardware design
10 years exp. ASIC development. MSU professor.
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
Senior Design Engineer at NASA-Goddard., Greenbelt, MD
Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,
i have done PGDMA in ASIC Design in physical design domain , from RV-VLSI Bangalore.
Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.
I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
4+ years of VLSI Backend experience. Working as Physical Design Engineer. Expertise in Analog layouts, physical verification and Physical Design. Open to learn and explore other domains of VLSI design.
José T. de Sousa holds a PhD degree from Imperial College London (1998) and has been a university lecturer and researcher at Lisbon University (1999-present). He holds 4 international patents, is co-author of one book, and was General Chair of the Field Programmable Logic and Applications Conference in 2013. Dr. de Sousa has published more than 70 technical papers in international journals and conferences. He was co-founder and CEO of Coreworks, a semiconductor intellectual property company, which he ran from 2001 to 2013. His specialties are digital circuit design, hardware/software architecture, technical team management and semiconductor IP marketing and sales.
Graduated with a Micro-electronics Master from Bordeaux university, France, I have now 18 years of experience. Worked in France, England, Belgium and Brazil, within 5 companies. Implemented physical design flows, recruited, trained and supervised trainees to experienced engineers, I have a vast experience in setting up complete flow (2 companies were startups), as well as signing off important design within NXP and CSR, all to successful first time right silicons. Able to work in total independence as well as within a team, I consider myself as optimist, result focused, with attention to detail while keeping a good trade between time to market and risk taking.
Principle Engineer at efabless corporation
Physical Design Engineer
Physical Design Engineer
Physical design engineer
Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.
An experimental physicist through sensor and instrumentation development.
Umer Imran is eager to work in the field of Computer Architecture and Memory Consistency. He is currently working as a Design Verification Engineer at Lampro Mellon, a training firm with the vision to transform Pakistan’s talent pool into leaders of RISC-V based SoC design. He constantly aims to gain expertise in the various domains of SoC Design including IP Design, ASICs, and low power architectures.
Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design. Fiction writer (National Literature Award for Novel, 2011, Costa Rica)
A young and ambitious individual, eager to apply my knowledge of Computer Architecture and VLSI Physical Design to develop hardware that is performance, power and area efficient, while actively contributing to the development and growth of the open-source semi-conductor industry
Managing Partner
Physical Design Engineer
Eduardo is an Electrical Engineer engaged in hardware development with a true passion for developing and enhancing applications. While at university, he worked in a variety of projects, from VHDL in a SOC project, to a PCB for a power circuit, and even web interfaces for electronic devices network connected. He allies his technical background with great communication skills. He is used to and is passionate about working in diverse cultural environment as was his period as an international student in Japan. He also got a certification in in Digital Integrated Circuit Design and Project Flow with Cadence tools (IC Brazil Program). Currently he works at HT Micron, and is interested in positions related to chip design, hardware design, embedded software development and similar areas.
A recent graduate student from Syracuse University major in Electrical Engineering with focus in VLSI Designs
Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.
I am an electronics engineer currently working as an intern in STMicroelectronics.
I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.
Edward Joullian Endowed Chair in Engineering Oklahoma State University Department of Electrical and Computer Engineering VLSI Computer Architecture Research Group
Assistant Professor (IISc) | Ph.D. & S.M. (MIT) | B.Tech. (IIT-KGP)
Motor control group at EE, UET strives to develop technologies in the domain of DC motor control, closed loop (PID) servo control, 3-phase AC (PMSM, ACIM) FOC control, targeting home appliances, industrial, robotic and EV applications.
I am a college student and want to do certain project work
student
BS EE from Stanford University and Digital Designer. Areas of focus are computer architecture, VLSI, and Analog IC. I am interested in making chips to test myself.
i am a college student and want to do projects
I'm a college student, want to do some project work
A researcher and VLSI guy
Kashif Inayat currently working as a doctorate fellow researcher at System-on-Chips (SoC) Laboratory, Electronics Engineering Department of Incheon National University, South Korea. He considers himself fortunate to have the opportunity to work under Prof. Jaeyong Chung at Incheon National University. Prior to starting his Ph.D., he completed his Master of Science in Electronics and Computer Engineering (ECE) from graduate school, Hongik University in 2019 under the supervision of Prof. Seong Oun Hwang. Moreover, during MS studies he worked at Information Security and Machine Learning Lab, Hongik University, South Korea as a graduate researcher for 2.5 years. Furthermore, he chaired the special sessions at International Conference on Green and Human Information Technology (ICGHIT 2019), held in Kuala Lumpur, Malaysia (Jan, 16-18, 2019). Moreover, he is a registered member of the Pakistan Engineering Council and a reviewer for the IEEE Access Journal.
I am student and wanted to improve my knowledge in VLSI
college student and want to do a certain project work.
myself Mohd Parvez Khan, I am pursuing btech from dtu in ECE.I have keen interest in VLSI and Digital domain.
I AM COLLEGE STUDENT AND I WANT TO DO CERTAIN PROJECTS ON IT
Digital design engineer Msc Student at cairo university Faculty of Engineering
A hard working IC Design master student aiming excellency and professional experience in the field of Integrated Circuit Design specially analog and mixed signal design like Data converters, LDO, Opamp and Bandgap reference.
Doctoral student at the Tokyo Institute of Technology.
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
Experienced SW developer (C/C++/C#) and digital HW designer (SoC/FPGA)
I am an Electrical Engineering working VLSI design farm with 7 tape-out experiences.
Current iOS Programmer, EE with decade of physical design experience in mixed signal - worked on POWER architecture PLLS.
SoC Architect.Technologist. Hands-on experience in complex low power SoC designs, from concept to production. Excellent track record in successful development and production of ASICs, Technologies: Bluetooth, WLAN, IoT, Gigabit Ethernet, EPON networks, Interface ICs, Broadcast TV and Communication controllers. Demonstrated consistent track record of first-pass silicon success. PhD in Low power VLSI. Recipient of US and Indian patents. Core Competency: Chip Architecture, Micro Architecture, logic design, RTL Verilog coding, Chip level verification, Static Timing analysis, Formal Verification, design rule checking, AXI, AHB and APB bus protocols, Digital ASIC methodology, DFT methodology, Low Power ASIC design, Interfacing with backend teams, Timing closure, Post silicon bring up and validation, Project Planning, Scheduling and Management, FPGA Prototyping. Author of Book "A Practical Approach to VLSI System on Chip (SoC) Design" published by Springer Nature. Domain experience: Communications, EPON, WLAN, Bluetooth, IoT, Healthcare, Nextgen TV, Automotive. Managed dynamic, cross cultural teams of size 40 to 100. Standards worked on IEEE802.3, IEEE802.11b, ac, ad. ATSE 3.0, Automotive ethernet, Bluetooth Quality standards: ISO 9002, ISO 13485, IEC 60601-2 Funded Research: Derivative Low power standard cell library development PhD Guidance: 2 one in Asynchronous VLSI design methodology and second in Sub 1V power supply for complex SoCs. Co-founded healthcare company:Sensesemi Technologies Pvt. Ltd. Academic research head and taught engineering students for their undergrad, Post grad and PhD courses Chair, IEEE NanoTechnology Council, Bangalore Section as a founder Chairperson, Current Senior IEEE member.
I am professor at Dept of EEE, BUET, Passionate to teach students IC Design and Fabrication Skill.
Experienced Senior Design Engineer with a demonstrated history of working in the electrical and electronic manufacturing industry. Skilled in DAC, SPICE, ADCs, Electronics Hardware Design, and Management. Strong engineering professional with a M-Tech focused in VLSI System Designs from Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering &Technology and also a B-Tech Degree in the field of Electrical, Electronics and Communications Engineering from Mahatma Gandhi Institute of Technology.
Master's research student in IC design has hands-on experience on Cadence tools like Virtuoso, Genus, Innovus, Calibre. Motivated to learn more in the field of IC design
Cryptography and security researcher at Seagate Technology
I am college student and I want to do some project work.
13+yr ASIC Digital Designer. Master degree on Microeletronic Sensors. Worked on NXP through different projects on automotive and consumer/general market MCUs on areas from SoC Integration to Timing Sign-Off
Digital System Designer.
Semiconductor professional with 12+ year experience in ASIC hardware design and methodology development. Main expertise is in chip STA signoff - top level, IO timing, High speed design timing, and good knowledge of RTL design, Physical design (Layout, CTS, Route, DRCs), Synthesis and Formal Verification. Have also completed business management studies and looking for interesting opportunities in chip product development and management.
Chip Design CAD Expert
Physical Design over 10 years, Front-End Design over 4 years, have knowledge on DFT, STA, ...
I am a student at IIIT Bangalore pursuing Integrated Mtech in Electronica and Communications Engineering and am fascinated about silicon wafers and want to pursue a career and build a revolution in this domain.
I am an electrical engineer
Physical Design Engineer at Laksh Semiconductors
college students, interested in project works for vlsi and memory design
Electrical Engineering student at UFMG, scheduled to graduate in Dec/2022. Experience in the automotive sector by the Formula Tesla UFMG team, designing electrical and electronic systems. Exchange experience in South Africa for 3 months studying English and working voluntarily in needy settlements. Currently, work as Software Engineer at Cadence Design Systems.
Senior Faculty Specialist at University of Maryland
I am a synthetic biologist and software engineer interested in chip design.
Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.
Independent Digital Design and Verification Expert with more than 20+ years of experience and founder of semify. While working for established semiconductor companies like Infineon, Dialog Semiconductor and NXP I was responsible for bringing ideas into working ASICs. I developed USound’s first ASIC from FPGA based prototyping to tapeout with minimal resourcing, demanding timeline and tight area and power consumption constraints. Currently I'm acting as a consultant for easyIC and Cypress / Infineon. In addition I'm is also lecturer at the FH Joanneum Graz and guest lecturer at the Technical University Graz.
An energetic semiconductor professional with varied experience in the field of research, teaching and IC design. 📌 More than 6 years of experience in analog and mixed signal IC design. 📌 3 years of mentoring experience in analog circuit and layout design. 📌 Been part of the 4 complete IC development project. 📌 Inventor and co-inventor of 2 patents (filed) in the field of high-speed data path communication. 📌 Published few research papers with more than 30 engineering citations. 📌 6 month experience as a lead role in standard cell library development in a leading semiconductor organisation. 📌 more than 4 years of teaching experience in under-graduate electronics engineering courses.
A digital design engineer, interested in memory hierarchies and high speed interfaces.
I’m an engineer always looking to learn, optimize and automate. I work on data analytics to provide deep insights into hardware designs, particularly physical design flow. Exploring areas to facilitate design engineers in taking data driven decisions for faster design turnaround times. I like to think about life. I like experimenting with different techniques (using software tools and meditation) to optimize my day and work effectively. In my free time, I’m learning Web Programming to build my own blog. I know there are templates and websites but where’s the fun and learning if you don’t do it from scratch? I like mentoring students on how to approach career and life in general.
Analog and Mixed Signals Engineering Students
Analog Design Engineer
Dad. Partner. Scientist. Activist. Maker. — He/His
For most of my career, I was a CAD technology innovator and CAD system architect at Intel Corporation. I signed up recently for a Udemy class called "VSD - Making the Raven Chip: How to Design a RISC-V SoC." The class pointed me to Efabless.
Dr Tapas Kumar Maiti, a former associate professor at Hiroshima University Japan, moved to DA-IICT India where he is a faculty member, since June 2019. He was a visiting faculty to IIEST-Shibpur. He has amazing research experience at McMaster University, Canada and IIT-Kharagpur. He has published more than 100 papers in reputed journals and conferences, and also co-authored a book. He received ICMM Excellent Presentation Award, IAAM Scientist Medal, and University Gold Medal. He is a member of IEEE, and Life Member of IEI. Currently, he is working in the areas of Intelligent Computing Devices, Robotics, and Cybernetics.
Osaze Shears is passionate about many engineering and computational concepts. These include embedded systems, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and microprocessor technologies. Osaze spends his free time tutoring other students who are interested in learning to become better computer scientists and engineers to benefit the greater society. Osaze is currently a PhD student at Virginia Tech conducting research under the Multifunctional Integrated Circuits and Systems (MICS) lab. His research interests include: • Spiking Neural Networks • Hardware Acceleration • SoC Design with ASICs and FPGAs • Deep Learning • Edge Computing
Enthusiastic VLSI Design Engineer currently working in Domain Specific Architectures
Semiconductor technologist with deep expertise in device fabrication and mixed signal circuit design for high-performance compute applications.
I'm currently a PhD candidate at Stanford studying Electrical Engineering with Prof. Priyanka Raina. I graduated from Princeton with high honors in Electrical Engineering and certificates in Applications of Computing and Engineering Physics. I completed my Stanford M.S. degree in EE; my current PhD research focuses on emerging memory/circuit technologies (resistive RAM/NEM relays) and efficient reconfigurable computing (FPGAs/CGRAs). I consider myself an eclectic learner who has never been satisfied to work in just a single area. In the past, I've done research projects across an extremely wide array of subjects, including oxide nanoelectronics (Prof. Patrick Irvin, Pitt), stochastic simulation of biochemical processes (Prof. Marcus Dittrich, PSC), deep learning applied to petroleum well data (Prof. Verena Kaynig-Fittkau, Harvard/QRI), and development of quantum cascade devices in group-IV materials (Prof. Claire Gmachl, Princeton). My senior thesis at Princeton with Prof. Prateek Mittal was focused on privacy threats posed by Content Delivery Networks. I've also worked as a software intern at two companies, GoFundMe and Amazon; there, I took on data science and analytics problems affecting business. Recently, I completed an (entirely virtual!) internship at NVIDIA focused on improving circuit design with AI. Additionally, I have several personal projects I'm proud of: an analytics engine for online Set! to understand how people learn the card game, enabling Amazon Alexa home assistants to rap battle each other, studying graph techniques for understanding musical collaborations... and so on. I love meeting/hearing ideas from new people, so feel free to contact me. Cheers!
I've done everything from silicon design at the "bottom of the stack" to System Architecture and Design (with plenty of SW to go with it; at every level)
"Architecting the dreams of a digital future, pixel by pixel, gate by gate."
Undergraduate student at Gebze Technical University, Turkiye. Works on custom instructions on Risc-v cores and Risc-v arthitechture.
EE PCB, Systems, Mechnical, Cooling, Power Used to sling a lot of gates (polygons) in esoteric processes (Gallium Arsenide, JJ)
Am so humble and respectful I want to achieve my dreams Faithfully
My name is Mohamed, I'm from Egypt, I'm studying at the electronics and communications engineering department at Cairo University, I'm an undergraduate student and my expected graduation year is 2024. I am interested in digital design track, I have done many projects related to this field. I am very passionate to get this experience and I am sure that I will do great work with you.
Leader of a quantum hardware engineering team. Quantum hardware engineer, IBM quantum administrator/ developer, carpenter from the countryside in northern Arizona.
i am very interested to learn about the Digital logic and its simulation
FPGA/HW engineer
VLSI DOMAIN SKILLS --------------------------- • Digital Electronics • HDL: Verilog • HVL: System Verilog • TB Methodology: UVM • Protocols: APB, UART, I2C, SPI • EDA Tools: Modelsim, Quartus Prime, Questasim. VLSI RTL SKILLS ---------------------- • Digital Skills : Combinational and Sequential circuits • FSM • Memories • Verilog : Data types • Operators • BA and NBA • Delays in Verilog • Begin-end and fork-join Blocks • System tasks and Function • Compiler directive • FSM Coding. VLSI VERIFICATION SKILLS ------------------------------------ • System Verilog HVL: Data Types • Memories • Interface • OOPS • Constraint Randomization • Threads • Functional coverage • CRCDV • SV Testbench (Hands on SV Testbench) • Universal Verification Methodology: UVM Objects and Components • UVM Factory • UVM Phases • UVM Configuration • TLM • Virtual Sequence and Sequencer • UVM Testbench (Hands on UVM Testbench).
Dedicated, innovative and enthusiastic individual with consolidated expertise in Digital Electronics, Data Sciences, Robotics and IoT. A confident leader who effectively collaborates with the team members to accomplish all goals in an accurate and timely manner.
A dedicated Physical Design Engineer aspiring to craft silicon for real-world applications.
I am into Analog and Mixed Signal designs. I have been involved in creating ASICs for 30 years.
ASIC Designer with experience in Back-end & Front-end stages for ASIC design flow.
Henry Duwe received his B.S. degree in computer engineering and computer science from the University of Wisconsin--Madison and his M.S. and Ph.D. in electrical and computer engineering (ECE) from the University of Illinois at Urbana-Champaign (UIUC). He is an Assistant Professor in the electrical and computer engineering (ECpE) department at Iowa State University. His research interests include computer architecture, compilers, design automation, and engineering education. He is focusing on the architecture and design of dependable and intelligent energy-harvesting computer systems. He advises the Chip ISU chip fabrication co-curricular.
I am a ASIC Designer with a piqued interest in AI Hardware Design.
Senior security researcher, compiler/binary hacker, NFC ninja, hardware hacker with a FPGA hammer. Previously Pay Security.
I am an alumnus of Masters in Electrical Engineering from Department of Electrical Engineering, University of Engineering and Technology, Lahore; the project should be shipped there. The address is: University of Engineering and Technology, Main Campus, G. T. Road, Lahore, Pakistan. Postal code: 39161
I'm a BTech Electronics and Instrumentation graduate and an electronics enthusiast who was inspired by the open-source silicon technology and it's accomplishment and aim to build a career for myself in VLSI specifically as an ASIC Physical Design Engineer.
Electronic engineer specialized in FPGA devices.
I am a final year Computer engineering student at Habib University. I am currently focused on in-depth study of RISCV architecture, and SoC design for Robots.
Since 2001 I have worked for a small IC Layout design firm located in Wilsonville, Oregon called Coast-to-Coast Layout Design Inc. We provide full-custom mask design services to big semiconductor partners, both digital and analog/mixed-signal. I began my career as a part-time Linux systems administrator, and was taught mask design by my mentor and boss, then over the past couple decades I moved up the ranks to my current GM position where I am responsible for most day-to-day operations and management of multiple mask design teams who are very highly valued by our customers that rely on our services to meet tough tapeout schedule and quality requirements. I'm here because I'm planning to use open-source EDA tools to help train new mask designers to help grow my company.
Greetings! I, Devang Sharma am a B.Tech final year student studying at Jaypee Institute, Noida. I am a VLSI-enthusiast and posses moderate to advanced-level skillset(at B.Tech level). I have studied about ASIC Design Flow and learnt several HDLs(Verilog, SV, UVM).
Experienced ASIC Digital Design and Physical Implementation Enthusiast
