I'm an AMS Design engineer. I like the IC design world and my recent goal is to be a scientist :)
Author of Yosys, IceStorm, PicoRV32, and other Open Source things
Developer of open source EDA tools on Open Circuit Design
I'm a staff member at efabless responsible for product management, business development, strategy, partnerships.
VLSI circuit design engineer with significant experience in microprocessor design in semiconductor processes from 65nm to 10nm. Provided register file designs and design training for Intel Big Core and SOC projects. Helped create semi-automated array layout methodology. Established cross-organizational methodology for variation analysis in register files. Converged memory IP handling across multiple organizations.
I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.
Embedded System Engineer
We’re supporting a community where more than millions of people learn, share, and work together to build a chip. At VSD, where we always promote “open source,” we’re promoting about a proven method of collaborating to create technology. The freedom to see the design, to learn from it, to ask questions and offer improvements: This is the open source way.
I am a digital design/verification engineer. I have 2 years of full-time industry experience. In total, I have 4.5 years of experience in RTL design, Electronic Design Automation and Verification using VHDL/Verilog, Perl, Tcl and Linux. I was the #1 graduate of Bahcesehir University in Mechatronics Engineering in 2013
I am a Application Engineer working for Cadence Design Systems and I facilitate the use of the Palladium Emulator at different Customers.
Principle Engineer at efabless corporation
Taher Kourany joined Scenario Design Services, Cairo, Egypt as a Senior IC Design Consultant in 2016. He received B.Sc Degree in electronics and communications engineering from Ain-Shams University, Cairo, Egypt, in 2012. He received M.S. degree in electronics from the American University, Cairo, Egypt, in 2015. Until October 2015 he was a Research Assistant with the Center of Nanoelectonics and Devices Research Labs at Zewail City for Science and Technology. Mr. Kourany has published papers in the field of time complexity reduction algorithms of floorplan representations, area and wirelength minimization, Pareto-front multi-objective optimization algorithms of highly chaotic systems. His current research interests include high linearity Power Amplifiers, time complexity reduction algorithms, data structures, parameters estimation of highly chaotic systems, and the synthesis of analog IC design and layout.
