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"profiles" search for "area_of_expertise": Digital-BE

Number of Results: 7

Matthew Ernest

VLSI circuit design engineer with significant experience in microprocessor design in semiconductor processes from 65nm to 10nm. Provided register file designs and design training for Intel Big Core and SOC projects. Helped create semi-automated array layout methodology. Established cross-organizational methodology for variation analysis in register files. Converged memory IP handling across multiple organizations.

Rama Kotapally

I have 20 years of experience in Circuit Design, Physical Design, RTL.


I am Layout Design Engineer having experience of 9+ years on SRAM layouts.