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"profiles" search for "skills": UVM
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Number of Results: 23

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Santhosh

IP & SoC Verification Engineer

Skills

Perl System Verilog Verilog VHDL UVM

Area of Expertise

Digital: Verification SoC: Verification
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Amogh Avinash

Skills

C/C++ Computer Architecture System Verilog UVM Verilog

Area of Expertise

Academic: Student
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Harika

Skills

System Verilog UVM

Area of Expertise

Digital: Verification
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Ankit Agrawal

I am VLSI Design & Verification Engineer.

Skills

Aldec RivieraPro C/C++ Digital Electronics System Verilog UVM Verilog Xilinx ISE

Area of Expertise

Digital: RTL Digital: Verification SoC: Verification
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Y.Goutham Datta

BZZZZZZ

Skills

System Verilog UVM Verilog

Area of Expertise

Digital: RTL
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Husni Mahdi

System Architect Design Engineer

Skills

Cadence System Verilog UVM Verilog Vivado Xcelium

Area of Expertise

Digital: Verification
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Anurag Darbari

SubIP and SoC Design Verification Engineer. Extends to running Full Chip Emulation on Palladium and Protium Platforms.

Skills

System Verilog uvm Verilog

Area of Expertise

Digital: RTL SoC: Verification
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Zain Rizwan Khan

Research Associate at Micro Electronics Research Lab (MERL) working as a hardware design engineer.

Skills

C/C++ System Verilog UVM Verilog

Area of Expertise

Digital: RTL Digital: Verification
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Surendra Kumar

Skills

Python System Verilog Verilog UVM

Area of Expertise

Academic: Teaching Analog: Verification Digital: RTL Digital: Verification SoC: Verification
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Jair Garcia Lamont

Designer specialized on VLSI radiation tolerant architectures and circuits

Skills

System Verilog T-Spice Tanner L-Edit UVM-Functional Verification

Area of Expertise

Academic: Research Circuits: Communication Digital: RTL Digital: Verification
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Slim Msehli

Skills

System Verilog ASIC FPGA UVM UPF Mixed signal design AMS Real number modeling

Area of Expertise

Mixed signal design and verification
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Manuel Muro

Known since I was 12 years old that I wanted to be an electrical engineer, by the time I was like 14 or 16 years I knew that I specifically wanted to design microprocessors. I officially became an electrical engineer by graduating with a B.S.E.E. along with a minor in Business from N.C. State University. With more than 30 years of industry experience, I look forward to bringing some of my own original ideas and visions into reality and I am very much tapped in the entrepreneurial spirit while also be an advocate for Open Source projects, both Software and hardware based, along with being a super advocate for the Agile movement for all engineering disciplines, i.e. beyond it just being a thing software folks do!

Skills

A-D/D-A AGILE AI AMBA ARM ASICs C/C++ Design Automation DSP FPGAs Full-Stack Dev JSON Memory(RRAM, SRAM, Flash & DRAM) Microprocessors MIPI-CSI MIPI-DSI MIPS ML PCIe Perl Python RF RISC-V SoCs Software Defined Radios UVM VLSI WISHBONE X86

Area of Expertise

Circuits: Memory Circuits: Microcontrollers
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RAHUL KUMAR

verification engineer

Skills

System Verilog Verilog uvm

Area of Expertise

Digital: Verification
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Deepak B

I'm an ASIC Design Engineer with a focus on SoC verification. With over three years of experience in the field, I have had the privilege of successfully completing and taping out three projects. My expertise lies in ensuring the functionality and performance of complex System-on-Chip designs through thorough verification methodologies. Throughout my career, I have gained a deep understanding of the entire design flow, from specification and architectural exploration to RTL coding and verification. I am proficient in industry-standard verification languages and methodologies, such as SystemVerilog and UVM.

Skills

C/C++ Cadence Virtuoso Matlab uvm

Area of Expertise

digital Digital: Verification SoC: Verification
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Ramesh Fernando

I'm a PhD student focusing on the Edge AI accelerators and Neuromorphic computing at Edge AI Acceleration Lab, Singapore University of Technology and Design

Skills

C/C++ System Verilog VCS UVM Verdi

Area of Expertise

Academic: Research
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Sunil Jalagam

Skills

System Verilog Verilog uvm

Area of Expertise

Academic: Student
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Ravi Teja

I am a results-driven Electrical Engineer with a strong foundation in digital design, RTL to GDSII flow, and system-level architecture, complemented by hands-on experience with FPGA and ASIC environments. With expertise in Verilog, SystemVerilog, and VHDL, I have designed and implemented advanced digital systems, including high-efficiency MLP architectures and custom ASIC designs for optimized performance and power efficiency

Skills

physical design Python uvm Verilog

Area of Expertise

Digital: Placement and Routing Digital: Synthesis System: Fabrication Process
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Mohd Rizwan

I am very dedicated to learn new things.

Skills

C/C++ System Verilog UVM Verilog

Area of Expertise

Digital: RTL
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VISHNU BAL.AJI

VLSI FRONT END DESIGN ENGINEER

Skills

C/C++ System Verilog UVM Verilog

Area of Expertise

Circuits: Microcontrollers Digital: RTL SOC SoC: Verification
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Naveen

Skills

Python System Verilog Verilog UVM C

Area of Expertise

Academic: Student Digital: RTL Digital: Synthesis Digital: Verification
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Mrunmayee

I am a recent graduate with a Major in Electronics and Telecommunication Engineering and a minor in computer engineering.

Skills

C/C++ Cadence Virtuoso Matlab Perl Python System Verilog Verilog VHDL uvm

Area of Expertise

Academic: Student Digital: RTL Digital: Verification
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Hemaprasad Kothainambi

Design Verification Engineer with a keen sense of interest in Computer Architecture and RTL Design

Skills

Cadence Virtuoso System Verilog UVM SVA

Area of Expertise

Digital: Verification
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Ramya Reddy

Skills

System Verilog Verilog VHDL uvm

Area of Expertise

Electronics