SubIP and SoC Design Verification Engineer. Extends to running Full Chip Emulation on Palladium and Protium Platforms.
Research Associate at Micro Electronics Research Lab (MERL) working as a hardware design engineer.
Designer specialized on VLSI radiation tolerant architectures and circuits
Known since I was 12 years old that I wanted to be an electrical engineer, by the time I was like 14 or 16 years I knew that I specifically wanted to design microprocessors. I officially became an electrical engineer by graduating with a B.S.E.E. along with a minor in Business from N.C. State University. With more than 30 years of industry experience, I look forward to bringing some of my own original ideas and visions into reality and I am very much tapped in the entrepreneurial spirit while also be an advocate for Open Source projects, both Software and hardware based, along with being a super advocate for the Agile movement for all engineering disciplines, i.e. beyond it just being a thing software folks do!
I'm an ASIC Design Engineer with a focus on SoC verification. With over three years of experience in the field, I have had the privilege of successfully completing and taping out three projects. My expertise lies in ensuring the functionality and performance of complex System-on-Chip designs through thorough verification methodologies. Throughout my career, I have gained a deep understanding of the entire design flow, from specification and architectural exploration to RTL coding and verification. I am proficient in industry-standard verification languages and methodologies, such as SystemVerilog and UVM.
I'm a PhD student focusing on the Edge AI accelerators and Neuromorphic computing at Edge AI Acceleration Lab, Singapore University of Technology and Design
I am a recent graduate with a Major in Electronics and Telecommunication Engineering and a minor in computer engineering.
Design Verification Engineer with a keen sense of interest in Computer Architecture and RTL Design
