Tag Search Results

Tag Search

"profiles" search for "area_of_expertise": SOC

Open Search

Number of Results: 284

Philipp Gühring

I am a software developer, trying to learn about hardware design

Skills

C/C++ Circuit Design Magic CAD ngspice Perl Python Software Developer Tcl/Tk Verilog

Area of Expertise

Business: PCB Manufacture CAD-Dev CAD: Scripting CAD: Tool Development Cryptography Miscellaneous: Cryptography Miscellaneous: Neural Networks Security SoC: ESD System: PCB

AZHAK ANWAR

Skills

C/C++ Matlab Python System Verilog Verilog FGPA

Area of Expertise

SoC: Verification System: FPGA Programming System: Test Programming

Nguyen Dao

Skills

Cadence Encounter Cadence Virtuoso Spectre Verilog

Area of Expertise

Academic: Research Analog: Design Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Mohamed Bamakhrama

Skills

C/C++ Python System Verilog System-C Verilog VHDL

Area of Expertise

Digital: RTL SoC: ESD

Jayakumar Janarthanam

20+ Years of Experience in Chip Design

Skills

Cadence Encounter Cadence Virtuoso Calibre Leadership Verilog

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning System: Fabrication Process System: Packaging

Tim Edwards

Developer of open source EDA tools on Open Circuit Design

Skills

Analog CMOS Circuit Analog IC Design Analog/Digital Circuit Design C/C++ Circuit Design Matlab Python Software Developer Verilog VLSI/ASIC and SoC Development

Area of Expertise

Analog Analog IC Analog IC Design Analog-Layout Analog-Mixed Signal-DV Analog-Simulation Analog-Verification ASIC Design/Verification Automatic Circuit Design CAD-Dev CAD-Scripts Communication and Signal Processing Cryptography Design Automation Digital-DFT Evolutionary algorithm signal processing SOC-DV SOC-ESD SOC-Packaging System-PCB System-Signal-Integrity Analog-ADC Analog-LDO Digital-BE Digital-DV Digital-RTL System-DSP System-Filters

Sun

Engineer, who typically worked in start up environment. So do A-Z, a-z and 1 - infinity if something has to work

Skills

C/C++ Verilog VLSI/ASIC and SoC Development

Area of Expertise

ASIC Design/Verification Communication and Signal Processing signal processing SOC-DV Digital-DV Digital-RTL

Srikanth Sundararajan

Skills

VLSI/ASIC and SoC Development

Area of Expertise

SOC-Packaging

Stepan Sutula

I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.

Skills

Analog CMOS Circuit Analog Analog IC Design Analog/Digital Circuit Design C/C++ Circuit Design Matlab Python Software Developer Verilog VLSI/ASIC and SoC Development

Area of Expertise

Analog Analog IC Analog IC Design Analog-Amplifiers Analog-Layout Analog-Mixed Signal-DV Analog-Modeling Analog-Simulation Analog-Verification ASIC Design/Verification Automatic Circuit Design CAD-Dev CAD-Scripts Communication and Signal Processing Design Automation Industrial Engineering signal processing SOC-DV SOC-Packaging System-PCB System-Power-Integrity System-Signal-Integrity Analog-ADC Analog-LDO Digital-DV System-Filters

SAKTHIVEL SM

VLSI PROFESSIONAL

Skills

C/C++ Circuit Design Matlab Verilog VLSI/ASIC and SoC Development

Area of Expertise

Cryptography Digital-DFT SOC-DV

MADHUSHREE

Skills

Analog CMOS Circuit Analog/Digital Circuit Design C/C++ Perl Verilog VLSI/ASIC and SoC Development

Area of Expertise

ASIC Design/Verification SOC-DV Digital-DV Digital-RTL

Rupesh

I am working into Soc verification

Skills

Verilog

Area of Expertise

SOC-DV

Shri Prakash

Skills

Python Verilog VLSI/ASIC and SoC Development

Area of Expertise

SOC-DV Digital-RTL

Balaraju

iam presently working as an Soc verification Engineer

Skills

Verilog

Area of Expertise

SOC-DV

Nishant Pani

Skills

Verilog

Area of Expertise

SOC-DV

Janak

Skills

Perl Verilog VLSI/ASIC and SoC Development

Area of Expertise

ASIC Design/Verification SOC-DV Digital-DV

Deepak Siddharth Parthipan

I am Digital/SoC Design and Verification enthusiast.

Skills

C/C++ Noob Perl Verilog VLSI/ASIC and SoC Development

Area of Expertise

Digital-DFT SOC-DV Digital-DV Digital-RTL

jatindersingh

Skills

Analog/Digital Circuit Design C/C++ Electric CAD Magic CAD ngspice Python System Verilog System-C Tcl/Tk Verilog VHDL VLSI/ASIC and SoC Development

Area of Expertise

Analog-SMPS Analog: Simulation Analog: Verification Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital-DV Digital-RTL Digital: DFT Digital: Placement and Routing Miscellaneous: Neural Networks SOC-DV SoC: ESD SoC: Floorplanning SoC: Verification System-DSP System: Chip Editing System: FPGA Programming

Josep Maria Sánchez Chiva

Current working in my PhD at BarcelonaTech.

Skills

Cadence Virtuoso Calibre Python Spectre VHDL

Area of Expertise

Academic: Research Analog: Design Analog: Layout Analog: Simulation Circuits: Sensors SoC: Floorplanning System: FPGA Programming System: PCB

eldho george

Skills

Cadence Virtuoso Matlab Perl System Verilog Verilog

Area of Expertise

Digital: RTL Digital: Verification SoC: Verification

Hossam Hassan

Skills

C/C++ Cadence Encounter Cadence Virtuoso Matlab Python System Verilog System-C Verilog

Area of Expertise

Academic: Research Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Circuits: Microcontrollers Circuits: Sensors Circuits: Signal Processing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: FPGA Programming System: PCB

bhavik balwani

i am working as physical design engineer

Skills

Cadence Encounter

Area of Expertise

SoC: Floorplanning

Luc Wong

I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".

Skills

C/C++ Cadence Encounter Cadence Virtuoso Eldo Matlab Perl Python Software Developer Spectre SPICE Opus System Verilog Tcl/Tk Verilog VHDL

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Neural Networks SoC: ESD SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: PCB System: Power Integrity System: Signal Integrity System: Test Equipment System: Test Programming

Preetham Lakshmikanthan

Skills

C/C++ System Verilog

Area of Expertise

Circuits: Power Management Digital: Verification SoC: Verification

Jyothisha

Skills

Cadence Encounter

Area of Expertise

SoC: Floorplanning

Praneeth

Skills

Cadence Encounter Cadence Virtuoso Hercules Perl Spectre Tcl/Tk Verilog VHDL

Area of Expertise

Circuits: Memory Circuits: Power Management Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning

Owais Farooq

Skills

C/C++ Python System Verilog Verilog

Area of Expertise

Digital: DFT Digital: RTL Digital: Verification SoC: Verification

Pushkaraksha K M

Physical design engineer with strong expertise in CAD and low power methodologies

Skills

Cadence Encounter Python Tcl/Tk Verilog

Area of Expertise

CAD: Tool Development Digital: Placement and Routing SoC: Floorplanning

Salvatore M. Cherchi

Skills

C/C++ Eagle CAD Electric CAD Matlab ngspice Python System Verilog

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Business: Design Services Circuits: Communication Circuits: Memory Circuits: Signal Processing Miscellaneous: Cryptography SoC: ESD SoC: Floorplanning System: Fabrication Process System: Power Integrity System: Signal Integrity

Mahmoud Youssuf Ahmad

Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Eagle CAD Matlab Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research Analog: Design Analog: Layout CAD: Scripting Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning System: FPGA Programming

Paulo Roberto Bueno de Carvalho

Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.

Skills

C/C++ Cadence Encounter Python System Verilog Verilog VHDL

Area of Expertise

Circuits: Communication Circuits: Filters Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification SoC: Floorplanning SoC: Verification System: FPGA Programming System: PCB

Bob Ledzius

35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.

Skills

C/C++ Leadership Matlab System Verilog Tcl/Tk Verilog

Area of Expertise

Business: Design Services Business: Management Business: Patents CAD: Scripting CAD: Tool Development Circuits: Filters Circuits: Microcontrollers Circuits: Signal Processing Digital: RTL Digital: Verification Miscellaneous: Cryptography SoC: Verification System: FPGA Programming System: PCB

Nambi

Skills

C/C++ ngspice Python System Verilog Tcl/Tk Verilog

Area of Expertise

Analog: Verification Business: Design Services CAD: Tool Development Digital: Verification SoC: Verification

ardencaple

Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.

Skills

C/C++ Leadership Python Verilog VHDL DC PrimeTime

Area of Expertise

CAD: Scripting Circuits: Filters Circuits: Microcontrollers Circuits: Signal Processing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: Fabrication Process System: FPGA Programming Digital audio IoT Soc Mixed Signal

Santhosh

IP & SoC Verification Engineer

Skills

Perl System Verilog Verilog VHDL UVM

Area of Expertise

Digital: Verification SoC: Verification

Mauricio De Carvalho

Skills

C/C++ Cadence Encounter Software Developer System Verilog Verilog VHDL

Area of Expertise

Business: Design Services Circuits: Microcontrollers Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: FPGA Programming

fabien andrade

Graduated with a Micro-electronics Master from Bordeaux university, France, I have now 18 years of experience. Worked in France, England, Belgium and Brazil, within 5 companies. Implemented physical design flows, recruited, trained and supervised trainees to experienced engineers, I have a vast experience in setting up complete flow (2 companies were startups), as well as signing off important design within NXP and CSR, all to successful first time right silicons. Able to work in total independence as well as within a team, I consider myself as optimist, result focused, with attention to detail while keeping a good trade between time to market and risk taking.

Skills

Cadence Encounter Leadership Tcl/Tk

Area of Expertise

CAD: Scripting Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Chuan Le

Skills

Cadence Encounter Leadership Synopsys Physical design

Area of Expertise

Digital: Placement and Routing SoC: Floorplanning

HALIM

Lecturer UiTM

Skills

System Verilog Tanner L-Edit Verilog

Area of Expertise

Academic: Teaching Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning

RASHMI

Physical Design Engineer

Skills

C/C++ Calibre Matlab Tcl/Tk VHDL

Area of Expertise

Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

RAJA KUMAR MEHTA

Physical Design Engineer

Skills

C/C++ Calibre System Verilog Tcl/Tk Verilog

Area of Expertise

Analog: Design Analog: Layout Analog: Verification Business: Management Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Pascal Buchschacher

designing mixed-mode ASICs since 1986 :-)

Skills

Cadence Virtuoso Leadership Matlab Spectre Verilog VHDL

Area of Expertise

Academic: Research Academic: Teaching Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification SoC: Verification

Vishal Prafulkumar Katigar

Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)

Skills

C/C++ Perl System Verilog Verilog VHDL

Area of Expertise

Circuits: Microcontrollers Circuits: Sensors Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: PCB

Stephane Badel

Physical design engineer

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Diva Eldo Hercules Matlab ngspice Octave Perl SKILL Spectre System Verilog Tcl/Tk Verilog

Area of Expertise

Analog: Layout Analog: Simulation CAD: Scripting CAD: Tool Development Circuits: Memory Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Sagar Jadhav

Skills

System Verilog Verilog

Area of Expertise

Digital: Verification SoC: Verification

Camillo

Experienced Analog Design Engineer with strong background in HV CMOS ASICs.

Skills

C/C++ Cadence Virtuoso Calibre Matlab Octave Perl Python SKILL Spectre

Area of Expertise

Academic: Research Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Circuits: Power Management SoC: ESD SoC: Floorplanning System: PCB

Marco Merlin

Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.

Skills

C/C++ Cadence Virtuoso Eagle CAD Matlab Octave Python SKILL System Verilog Verilog VHDL wifi bluetooth LTE

Area of Expertise

Analog: Verification Circuits: Communication Circuits: Microcontrollers Circuits: Sensors Circuits: Signal Processing Digital: RTL Digital: Verification Miscellaneous: Neural Networks SoC: Verification System: PCB System: Test Equipment System: Test Programming

Fenil

Skills

Cadence Encounter Tcl/Tk

Area of Expertise

Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

MUVVA LAKSHMANKUMAR

Skills

C/C++ Cadence Encounter Perl Tcl/Tk Verilog

Area of Expertise

Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Sushma kumari

Skills

Cadence Encounter

Area of Expertise

Digital: Placement and Routing Digital: Verification SoC: Floorplanning

Umer Imran

Umer Imran is eager to work in the field of Computer Architecture and Memory Consistency. He is currently working as a Design Verification Engineer at Lampro Mellon, a training firm with the vision to transform Pakistan’s talent pool into leaders of RISC-V based SoC design. He constantly aims to gain expertise in the various domains of SoC Design including IP Design, ASICs, and low power architectures.

Skills

C/C++ Matlab Python System Verilog Tcl/Tk Verilog

Area of Expertise

Digital: Verification SoC: Verification

Pengyu Wei

Skills

Cadence Virtuoso Matlab Octave

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling SoC: ESD System: PCB System: Test Equipment

Komal Javed

A young and ambitious individual, eager to apply my knowledge of Computer Architecture and VLSI Physical Design to develop hardware that is performance, power and area efficient, while actively contributing to the development and growth of the open-source semi-conductor industry

Skills

Leadership Matlab Octave System Verilog Tcl/Tk Verilog

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning

Ira Chayut

Skills

C/C++ Verilog

Area of Expertise

Circuits: Microcontrollers Circuits: Signal Processing Digital: RTL SoC: Verification

Ankit Agrawal

I am VLSI Design & Verification Engineer.

Skills

Aldec RivieraPro C/C++ Digital Electronics System Verilog UVM Verilog Xilinx ISE

Area of Expertise

Digital: RTL Digital: Verification SoC: Verification

Menaka Sajjan

Skills

Cadence Encounter Cadence Virtuoso Perl Verilog VHDL

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: ESD

MAYANK VASHISHT

Interested in Design, Verification, and Hand-off of Analog IPs. Worked on the definition, modeling, design, verification of DC-DC converters, Chargers, Ideal-Diodes, LDOs, Regulators, Bandgap references, Current limiting and sensing architectures. Excited for challenges in Analog Design, Layout and Post-silicon verification.

Skills

Cadence Virtuoso Matlab Octave SKILL Spectre System Verilog Verilog

Area of Expertise

Analog: Design Analog: Modeling Analog: Simulation Analog: Verification Circuits: Filters Circuits: Power Management Circuits: Signal Processing Digital: Verification SoC: ESD System: Test Programming

Azhar Din

Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.

Skills

Cadence Virtuoso Calibre Diva Leadership Matlab Perl Spectre

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Management CAD: Scripting Circuits: Communication Circuits: Filters Circuits: Power Management Circuits: Sensors SoC: ESD SoC: Floorplanning SoC: Verification System: Fabrication Process System: PCB System: Test Equipment

CHINTADA.GAYATRI

Physical Design Engineer

Skills

C/C++ Calibre System Verilog Tcl/Tk Verilog

Area of Expertise

Analog: Design Analog: Layout Analog: Verification Business: Management Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Ronan BARZIC

Principal Engineer at ONiO AS

Skills

C/C++ Magic CAD ngspice Python System-C Verilog

Area of Expertise

CAD: Scripting Circuits: Power Management Digital: RTL Digital: Verification Miscellaneous: Neural Networks SoC: Verification

Gautam Navapara

Skills

C/C++ Cadence Encounter Calibre Magic CAD Perl Tcl/Tk

Area of Expertise

Digital: Placement and Routing SoC: Floorplanning SoC: Verification

David Garner

An experienced mixed-signal IC design engineer / design manager with over 25 years experience. Has design and led the design of multiple mixed-signal ICs through to tapeout and silicon verification. Also experienced with the delivery of IP blocks. Worked across multiple market sectors.

Skills

Cadence Virtuoso Diva Leadership Matlab Octave SKILL Spectre

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Management Business: Patents Circuits: Communication Circuits: Filters Circuits: Power Management Circuits: Sensors Circuits: Signal Processing SoC: ESD SoC: Floorplanning SoC: Verification System: Chip Editing System: Fabrication Process System: Power Integrity System: Quality Assurance System: Signal Integrity System: Test Equipment

Amit Prakash Gonnagar

Skills

Cadence Encounter Cadence Virtuoso Calibre Electric CAD Magic CAD ngspice Perl Spectre System Verilog Tcl/Tk Verilog

Area of Expertise

Circuits: Power Management Digital: Placement and Routing Digital: Synthesis SoC: ESD SoC: Floorplanning System: Chip Editing System: Fabrication Process System: PCB System: Power Integrity System: Signal Integrity System: Test Programming

Lakshya Kailkhura

Skills

Cadence Encounter

Area of Expertise

CAD: Scripting Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification SoC: ESD SoC: Floorplanning System: Signal Integrity

Larry Pearlstein

ASIC architect and designer. Specialize in deep learning, video, image and signal processing, and compression. Professor of Electrical and Computer Engineering at The College of New Jersey.

Skills

C/C++ Eagle CAD Matlab Octave Perl Python Software Developer System Verilog System-C Verilog VHDL

Area of Expertise

Academic: Teaching Analog: Design Business: Patents Circuits: Memory Circuits: Microcontrollers Circuits: Signal Processing Digital: RTL Digital: Verification Miscellaneous: Neural Networks SoC: Verification System: FPGA Programming System: PCB System: Test Equipment

gb6612

Skills

C/C++ Cadence Virtuoso Leadership ngspice Perl System Verilog Verilog

Area of Expertise

Business: Management Digital: RTL Digital: Synthesis Digital: Verification SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: Quality Assurance

Pam

Learning, is growing

Skills

Cadence Virtuoso

Area of Expertise

Digital: DFT Digital: Verification SoC: Verification System: Test Programming

Kranthi Kiran Konganti

Skills

C/C++ Cadence Virtuoso System Verilog Verilog

Area of Expertise

Analog: Design Analog: Verification Digital: RTL Digital: Verification SoC: Verification

KHADIJA FAHR

Skills

Verilog

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning System: Signal Integrity

Utsav Banerjee

Assistant Professor (IISc) | Ph.D. & S.M. (MIT) | B.Tech. (IIT-KGP)

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Eagle CAD Matlab ngspice Perl Python Spectre System Verilog Tcl/Tk Verilog

Area of Expertise

Academic: Research Academic: Teaching Analog: Design Analog: Layout Analog: Simulation CAD: Scripting Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography Miscellaneous: Neural Networks SoC: Floorplanning System: FPGA Programming System: PCB System: Test Equipment

Sanjitha Kurugunta

I am Physical Designe Engineer -1 at Signoff Semiconductors

Skills

Physical Design

Area of Expertise

Digital: Placement and Routing SoC: Floorplanning

João Silva

PhD Student Research on Integrated Sensor Interfacing Systems featuring signal conditioning and A/D conversion. Functional blocks developed: VGA, current-steering DAC, SAR ADC, AA Filters, SPI master/slave.

Skills

C/C++ Cadence Virtuoso Calibre Eagle CAD Python Verilog

Area of Expertise

Academic: Research Academic: Student Analog: Design Analog: Layout Analog: Simulation Circuits: Sensors Circuits: Signal Processing SoC: Floorplanning SoC: Verification System: PCB System: Test Equipment

Nishit Nathwani

I am a Master's student who has to know for learning and do experiments as well as for writing technical blogger. My website links are given below to connect with my open-source family of the VLSI champions. https://nishitnathwani.blogspot.com/ https://geniusvlsi.blogspot.com/

Skills

Cadence Virtuoso Eagle CAD Matlab Netgen ngspice Python Spectre Verilog VHDL

Area of Expertise

Academic: Teaching Analog: Design Analog: Simulation Circuits: Sensors Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning System: FPGA Programming

Cyril Prasanna Raj Premkumar

Professor and Entrepreneur

Skills

Cadence Virtuoso

Area of Expertise

SoC: Floorplanning

Asma Mohsin

Skills

C/C++ Matlab Verilog VHDL

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning System: FPGA Programming

Dhanabal Shanmugam

Skills

System Verilog

Area of Expertise

CAD: Tool Development Digital: Verification SoC: Verification System: FPGA Programming

Priyanka Dutta

current Phd Student in UCSC Hardware System Collective group formerly worked in Qualcomm Wireless R&D team as a design verification engineer

Skills

Python System Verilog Verilog VHDL

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification

Matthew Guthaus

Professor of CSE at UC Santa Cruz

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Magic CAD Netgen ngspice Python Software Developer Verilog

Area of Expertise

Academic: Research Academic: Teaching CAD: Tool Development Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning System: Fabrication Process System: PCB

Sergi Xabier Albort Vergés

Skills

Cadence Virtuoso VHDL

Area of Expertise

Analog: Layout Digital: Placement and Routing SoC: Floorplanning

Manu Mathew

Skills

C/C++ Cadence Encounter Cadence Virtuoso System Verilog Verilog

Area of Expertise

Academic: Research Academic: Student SoC: Floorplanning

Ray Xue

Skills

C/C++ System Verilog

Area of Expertise

SoC: Verification

igor ignjic

Skills

C/C++ Eagle CAD Leadership Matlab Perl System Verilog System-C Tcl/Tk Verilog VHDL

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: FPGA Programming

Joel Åhlund

Skills

C/C++ Cadence Virtuoso Eagle CAD Electric CAD Matlab Python Tcl/Tk Verilog VHDL

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Business: PCB Manufacture CAD: Scripting Circuits: Communication Circuits: Memory Circuits: Microcontrollers Circuits: Sensors Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis Miscellaneous: Neural Networks SoC: Floorplanning System: FPGA Programming System: PCB System: Power Integrity System: Test Programming

Mark Ewert

Skills

C/C++ Python System-C Tcl/Tk Verilog

Area of Expertise

SoC: Floorplanning System: Chip Editing

D Va

Skills

Verilog

Area of Expertise

SoC: Verification

KASHIF INAYAT

Kashif Inayat currently working as a doctorate fellow researcher at System-on-Chips (SoC) Laboratory, Electronics Engineering Department of Incheon National University, South Korea. He considers himself fortunate to have the opportunity to work under Prof. Jaeyong Chung at Incheon National University. Prior to starting his Ph.D., he completed his Master of Science in Electronics and Computer Engineering (ECE) from graduate school, Hongik University in 2019 under the supervision of Prof. Seong Oun Hwang. Moreover, during MS studies he worked at Information Security and Machine Learning Lab, Hongik University, South Korea as a graduate researcher for 2.5 years. Furthermore, he chaired the special sessions at International Conference on Green and Human Information Technology (ICGHIT 2019), held in Kuala Lumpur, Malaysia (Jan, 16-18, 2019). Moreover, he is a registered member of the Pakistan Engineering Council and a reviewer for the IEEE Access Journal.

Skills

C/C++ Leadership Matlab Python Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research Academic: Student Business: Design Services CAD: Scripting Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: Power Integrity

Alexandre Moriceau

Skills

Python Tcl/Tk Verilog VHDL

Area of Expertise

SoC: Verification

Manish Kumar Mahato

Skills

C/C++ Cadence Encounter Cadence Virtuoso Matlab Python Software Developer System Verilog Verilog

Area of Expertise

Academic: Research Business: PCB Manufacture Circuits: Memory Circuits: Microcontrollers Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Neural Networks SoC: Floorplanning SoC: Verification System: FPGA Programming System: PCB System: Test Equipment

Midhun M Pillai

Skills

Cadence Encounter Cadence Virtuoso Calibre Python Tcl/Tk Verilog

Area of Expertise

Digital: Placement and Routing Digital: Synthesis SoC SoC: Floorplanning

James Tandon

Skills

C/C++ Cadence Virtuoso Calibre Eagle CAD Eldo Leadership Magic CAD Matlab Octave Perl Python Scilab Software Developer System Verilog Verilog

Area of Expertise

Academic: Research Academic: Teaching Analog: Design Analog: Layout Analog: Simulation Business: Design Services CAD: Tool Development Circuits: Microcontrollers Digital: RTL Digital: Synthesis SoC: Floorplanning System: Chip Editing System: FPGA Programming System: PCB

Shankar Narayanan

Skills

physical design synopsys

Area of Expertise

SoC: Floorplanning

Komal Javed

Skills

Matlab Python System Verilog Verilog

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning

Yi Chung Chen

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Eagle CAD Electric CAD Magic CAD Netgen ngspice Perl Python SKILL Software Developer Spectre System Verilog Tanner L-Edit Tcl/Tk Verilog

Area of Expertise

Academic: Research Academic: Teaching Analog: Simulation CAD: Scripting CAD: Tool Development Circuits: Memory Circuits: Microcontrollers Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Neural Networks SoC: Floorplanning System: Fabrication Process System: FPGA Programming System: Test Equipment

Vaibhav Vishwakarama

Skills

C/C++ System Verilog Verilog VHDL

Area of Expertise

Digital: Verification SoC: Verification Design

Mitch Bailey

Developer of open source reliability verification system CVC(RV). https://github.com/d-m-bailey/cvc

Skills

C/C++ Calibre Netgen Python SKILL Software Developer

Area of Expertise

CAD: Scripting CAD: Tool Development SoC: Verification

Shinya Takeuchi

I like to make toys like flapping planes.

Skills

C/C++ Cadence Encounter Cadence Virtuoso Perl

Area of Expertise

Analog: Layout SoC: ESD

Ferhat Böcek

I am a 3rd year electronics engineering student. I am interested in chip design and want to learn this field. www.linkedin.com/in/ferhat-böcek-b73452170

Skills

Verilog VHDL

Area of Expertise

Academic: Student SoC: Floorplanning

Ajay Pai

Skills

Python System Verilog Verilog C

Area of Expertise

Digital: Verification SoC: Verification

Nicholas Molinski

Skills

C/C++ Electric CAD Matlab ngspice Python Software Developer Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Neural Networks SoC: Floorplanning SoC: Verification System: FPGA Programming System: PCB System: Power Integrity System: Signal Integrity System: Test Programming

Tony Chan

30+ years in IC design, completed several NOR/NAND flash projects, and running in production.

Skills

Cadence Virtuoso Calibre Leadership Python

Area of Expertise

Circuits: Memory SoC: ESD SoC: Floorplanning

veena S Chakravarthi

SoC Architect.Technologist. Hands-on experience in complex low power SoC designs, from concept to production. Excellent track record in successful development and production of ASICs, Technologies: Bluetooth, WLAN, IoT, Gigabit Ethernet, EPON networks, Interface ICs, Broadcast TV and Communication controllers. Demonstrated consistent track record of first-pass silicon success. PhD in Low power VLSI. Recipient of US and Indian patents. Core Competency: Chip Architecture, Micro Architecture, logic design, RTL Verilog coding, Chip level verification, Static Timing analysis, Formal Verification, design rule checking, AXI, AHB and APB bus protocols, Digital ASIC methodology, DFT methodology, Low Power ASIC design, Interfacing with backend teams, Timing closure, Post silicon bring up and validation, Project Planning, Scheduling and Management, FPGA Prototyping. Author of Book "A Practical Approach to VLSI System on Chip (SoC) Design" published by Springer Nature. Domain experience: Communications, EPON, WLAN, Bluetooth, IoT, Healthcare, Nextgen TV, Automotive. Managed dynamic, cross cultural teams of size 40 to 100. Standards worked on IEEE802.3, IEEE802.11b, ac, ad. ATSE 3.0, Automotive ethernet, Bluetooth Quality standards: ISO 9002, ISO 13485, IEC 60601-2 Funded Research: Derivative Low power standard cell library development PhD Guidance: 2 one in Asynchronous VLSI design methodology and second in Sub 1V power supply for complex SoCs. Co-founded healthcare company:Sensesemi Technologies Pvt. Ltd. Academic research head and taught engineering students for their undergrad, Post grad and PhD courses Chair, IEEE NanoTechnology Council, Bangalore Section as a founder Chairperson, Current Senior IEEE member.

Skills

Cadence Encounter System Verilog Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research Academic: Teaching Circuits: Communication Circuits: Power Management Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: Chip Editing

Huy Le

Skills

HDL SOC

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: FPGA Programming

Ronaldo Enrique Serrano Peña

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Eagle CAD Python Tcl/Tk Verilog

Area of Expertise

Academic: Research Digital: Placement and Routing Digital: RTL Digital: Verification Miscellaneous: Cryptography SoC: Floorplanning SoC: Verification System: PCB

zhang xin

Skills

Cadence Virtuoso Calibre Hercules Perl Spectre

Area of Expertise

Analog: Layout Analog: Modeling Analog: Simulation Business: Design Services Business: Foundry Services CAD: Scripting CAD: Tool Development SoC: ESD SoC: Floorplanning SoC: Verification

Arafat Bouchafra

I'm a software engineer (operating systems architect), and a microelectronics engineer (IC designer)

Skills

C/C++ Python java go rust Linux

Area of Expertise

Circuits: Microcontrollers Miscellaneous: Neural Networks SoC: Floorplanning

Zong-Ru Li

2nd year MS student in ECE, looking for joining an ASIC project.

Skills

C/C++ Python System Verilog Tcl/Tk Verilog

Area of Expertise

Academic: Student CAD: Scripting Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification

Albert Zick Olympus

Skills

C/C++ Python System Verilog Verilog

Area of Expertise

Academic: Research Digital: RTL SoC: Verification

amartya saha

Skills

Cadence Virtuoso Python Scilab Tcl/Tk VHDL

Area of Expertise

Analog: Layout Analog: Simulation Analog: Verification CAD: Scripting Circuits: Power Management SoC: Verification System: Chip Editing

Brajesh

Skills

Cadence Virtuoso Calibre Eldo ngspice Spectre Tcl/Tk Verilog

Area of Expertise

Academic: Research Academic: Teaching Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification SoC: Floorplanning System: FPGA Programming System: Test Equipment

Jafar Hussain

IC Designer

Skills

C/C++ Cadence Virtuoso Calibre Matlab Spectre System Verilog Verilog

Area of Expertise

Academic: Student Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification SoC: Floorplanning System: Fabrication Process

Alfred Tse

Skills

System Verilog Verilog VHDL tcl

Area of Expertise

Digital: RTL Digital: Verification SoC: Verification SoC

Amartya Saha

Skills

Cadence Virtuoso Matlab Octave Python Tcl/Tk Verilog VHDL

Area of Expertise

CAD: Scripting CAD: Tool Development Circuits: Filters Circuits: Memory Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: Chip Editing System: Fabrication Process System: Power Integrity System: Signal Integrity

Marco Crescentini

Skills

C/C++ Cadence Virtuoso Calibre Eldo Matlab Spectre

Area of Expertise

Academic: Research Academic: Teaching Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Circuits: Sensors Circuits: Signal Processing Digital: DFT SoC: Floorplanning System: Chip Editing System: Power Integrity System: Signal Integrity System: Test Equipment System: Test Programming

Shruti Prakash Gupta

I am a Senior Undergraduate in Electrical Engineering Department at IIT Gandhinagar, India. VLSI Design and the ability to tweak at the hardware level interest me a lot!

Skills

C/C++ Cadence Virtuoso Matlab Python System Verilog Verilog

Area of Expertise

Academic: Student CAD: Scripting Circuits: Microcontrollers Digital: RTL Digital: Verification SoC: Verification System: FPGA Programming

Pradeep Purushothaman Vadakkodathu

Skills

C/C++ Matlab System Verilog Tanner L-Edit Tcl/Tk Verilog

Area of Expertise

Digital: RTL Digital: Verification SoC: Verification System: FPGA Programming

Mustafa Khairallah

Cryptography and security researcher at Seagate Technology

Skills

C/C++ Cadence Encounter Matlab Octave perl Python Software Developer System Verilog Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research CAD: Scripting Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography SoC: Verification

Sergi Xabier Albort Vergés

Skills

Cadence Virtuoso Calibre

Area of Expertise

Academic: Student Digital: Placement and Routing SoC: Floorplanning

Charles Hu

RF/Analog IC design and SOC

Skills

Cadence Virtuoso Calibre Python System Verilog RF EMX ADS

Area of Expertise

Analog: Design Analog: Simulation Business: Design Services Business: Packaging Circuits: Communication Circuits: Power Management SoC: ESD SoC: Floorplanning System: Test Equipment System: Test Programming

Dinesh Annayya

Skills

C/C++ Python System Verilog Tcl/Tk Verilog

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification

Dave Keeshan

ASIC and FPGA design and verification Engineer with a sideline in bring devops to Hardware projects

Skills

Devops FPGA Python System Verilog VHDL

Area of Expertise

CAD: Scripting CAD: Tool Development Circuits: Memory Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography Miscellaneous: Neural Networks SoC: Verification System: FPGA Programming

Sharan R P

Fresher interested in asic physical design and looking for job opportunities in physical design engineering

Skills

Perl

Area of Expertise

Digital: Placement and Routing SoC: Floorplanning

David Mitchell Bailey

Open-source software developer with 30 years experience in back-end verification.

Skills

C/C++ Cadence Virtuoso Calibre Python SKILL Software Developer

Area of Expertise

CAD: Scripting CAD: Tool Development SoC: Verification

Yudhi

Skills

C/C++ Leadership Python Verilog VHDL

Area of Expertise

Business: Design Services CAD: Scripting Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification

Ajao Taiwo

Am a male from Lagos I attended simmic collage am in ss3 .am 19 year old live with my mom

Skills

SKILL

Area of Expertise

SoC: Verification

Krishna Sai Kanthan

Skills

C/C++ Cadence Virtuoso Perl System Verilog Tcl/Tk Verilog vim

Area of Expertise

Digital: Placement and Routing SoC: ESD System: Power Integrity

Nghi Thai

Physical Design over 10 years, Front-End Design over 4 years, have knowledge on DFT, STA, ...

Skills

Cadence Encounter Calibre Leadership Tcl/Tk Verilog

Area of Expertise

Academic: Student Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Sam Lim

I am a novice, building a Test chip for the first time

Skills

C/C++ Perl Python Software Developer Tcl/Tk Verilog

Area of Expertise

CAD: Scripting Digital: DFT Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: Fabrication Process System: FPGA Programming System: Quality Assurance System: Signal Integrity System: Test Equipment System: Test Programming

Jerry Cheng

Skills

Cadence Encounter Calibre Perl Python Tcl/Tk Verilog VHDL

Area of Expertise

CAD: Scripting Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: ESD SoC: Floorplanning System: Power Integrity

Nandagopal A

Skills

Leadership Tcl/Tk Verilog

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: FPGA Programming

SUJOY BISWAS

Experienced design verification hw engineer

Skills

Cadence Encounter Cadence Virtuoso Matlab Python System Verilog Verilog

Area of Expertise

Digital: RTL Digital: Verification SoC: Verification

Uttam Singhal

Skills

Cadence Encounter Cadence Virtuoso Calibre Leadership

Area of Expertise

SoC: Floorplanning

bill rivard

I am interested in new things. I've designed chips from definition to polygons, mostly in the pursuit of new capabilities.

Skills

Magic CAD spice Verilog

Area of Expertise

Academic: Research Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Business: Management Business: Patents Circuits: Power Management Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography Miscellaneous: Neural Networks SoC: ESD SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: PCB System: Signal Integrity

Antaryami Panigrahi

Skills

C/C++ Cadence Virtuoso Eagle CAD Scilab System Verilog Tanner L-Edit Verilog

Area of Expertise

Academic: Research Analog: Design Analog: Simulation Circuits: Communication Circuits: Power Management Digital: RTL Digital: Verification SoC: Verification

Joseph Kiniry

Dad. Partner. Scientist. Activist. Maker. — He/Him

Skills

Leadership

Area of Expertise

Academic: Research Academic: Teaching CAD: Tool Development Circuits: Microcontrollers Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography SoC: Verification System: FPGA Programming

Siva Bhanu Krishna Boga

Skills

C/C++

Area of Expertise

SoC: Verification

Abdul Wadood

Final year student of Electrical Engineering at UET Lahore. Area of expertise is Digital Design, Computer Architecture and SOCs.

Skills

Python System Verilog Verilog

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: ESD

Dr. Olivine

Skills

C/C++

Area of Expertise

SoC: Verification

E-Jen Lien

IC design Engineer

Skills

C/C++ Cadence Virtuoso Calibre Leadership Matlab Octave Perl Python Software Developer Spectre Verilog

Area of Expertise

Analog: Simulation Analog: Verification Business: Design Services Business: Patents CAD: Scripting CAD: Tool Development Circuits: Microcontrollers Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography SoC: Floorplanning SoC: Verification System: Chip Editing System: Fabrication Process System: FPGA Programming

Devender

Skills

Calibre

Area of Expertise

SoC: Verification

Sharath Hariharapura Subashchandra

Skills

Calibre Hercules Magic CAD Netgen Tcl/Tk Verilog VHDL

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: ESD SoC: Floorplanning System: Fabrication Process

Anand Bhatt

Skills

Cadence Encounter Cadence Virtuoso Calibre Perl SKILL

Area of Expertise

Analog: Layout Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning System: Power Integrity

Nagaraj Ananthapadmanabhan

Skills

Cadence Encounter Cadence Virtuoso Leadership Matlab Python Spectre Tanner L-Edit Verilog VHDL

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Management Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification SoC: ESD SoC: Floorplanning System: Fabrication Process System: Packaging System: PCB

amin savari

Skills

C/C++ System-C

Area of Expertise

Digital: Synthesis Digital: Verification SoC: Verification System: Fabrication Process

Katharina Ruep

Skills

C/C++ Cadence Virtuoso Matlab Python System Verilog Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research Academic: Teaching Circuits: Communication Digital: RTL Digital: Verification SoC: Verification

Abdul Moeez

Skills

C/C++ Verilog VHDL

Area of Expertise

Academic: Student Analog: Design Analog: Simulation Circuits: Microcontrollers Circuits: Sensors SoC: Verification System: FPGA Programming

Bill Flynn

Skills

C/C++ Python Tcl/Tk Verilog VHDL

Area of Expertise

Digital: RTL Digital: Verification SoC: Verification

Eric Fogleman

Skills

C/C++ Cadence Virtuoso Leadership Matlab ngspice Octave Python Spectre Tanner L-Edit Verilog

Area of Expertise

Analog: Design Circuits: Communication Circuits: Filters Circuits: Signal Processing Digital: RTL SoC: ESD SoC: Floorplanning

Xiaohu Zhu

Skills

C/C++ Python rust artificial intelligence

Area of Expertise

Academic: Research Miscellaneous: Neural Networks SoC: Verification

wu wen

Skills

C/C++

Area of Expertise

SoC: Verification

Akshay Revankar

Skills

C/C++ Cadence Virtuoso Verilog

Area of Expertise

Circuits: Microcontrollers Digital: RTL Digital: Verification SoC: Verification System: FPGA Programming

LOKESH BOGGARAPU

Automation enthusiast (likes to code in Perl). At this time, Doing Master's in VLSI Design and working as an intern @intel. Great learning experience doing both simultaneously. Have experience designing in both circuit (Low power & timing) & device level (high performance designs for digital applications). Obtained honor of 3rd position in concept design competition by ISRO for designing temperature & radiation resistant Tunnel FET. Would love to work with all device technology enthusiasts as opportunities arise.

Skills

Cadence Virtuoso Perl Python Verilog Sentaurus TCAD

Area of Expertise

Academic: Student CAD: Scripting Circuits: Signal Processing Digital: Verification SoC: Verification

Talha Bin Azmat

I am en Electronics Engineer currently Pursuing my Masters in IC design from FAST NUCES Islamabad.

Skills

C/C++ Cadence Virtuoso Calibre Magic CAD Matlab ngspice System Verilog

Area of Expertise

Analog: Design Analog: Layout Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning SoC: Verification

David Fleischer

Technology development in intergrated analog circuits. I'm available to design analog and mixed-signal circuits as an external contractor.

Skills

A/D converter Analog and mixed-signal IP circuit design Audio Bandgap reference CMOS Image Sensor Computer arithmetic Integration Nonvolatile memory Operational amplifier Sigma-delta SPICE simulations Video DAC

Area of Expertise

Academic: Research Academic: Teaching Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services Business: Patents Business: PCB Manufacture Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Miscellaneous: Cryptography SoC: Verification System: PCB

Ömer Cogal

Digital design and ASIC enthusiast.

Skills

C/C++ Cadence Encounter Cadence Virtuoso Python Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research Circuits: Filters Circuits: Microcontrollers Circuits: Sensors Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning System: FPGA Programming

Kali_Core

electronic system designer / software and hardware engineer, embeded system expert, signal expert, proccess designer, researcher, Developer of complexity and reversal wantings. Reverse engineer. i addopt my whole life to this science. thank you for presentings of quantum, psych

Skills

C/C++ Cadence Virtuoso Eagle CAD Electric CAD Leadership Software Developer Spectre System Verilog System-C Verilog VHDL

Area of Expertise

Academic: Research Analog: Design Analog: Modeling Analog: Verification Business: Design Services Business: PCB Manufacture Business: Public Relations Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: RTL Digital: Synthesis Miscellaneous: Cryptography Miscellaneous: Neural Networks SoC: ESD SoC: Verification System: Chip Editing System: FPGA Programming System: PCB System: Signal Integrity System: Test Programming

Zhiyang Ong

Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.

Skills

C/C++ Cadence Encounter Cadence NC-Verilog Cadence Virtuoso Electric CAD Electric VLSI Design System Matlab Mentor/Siemens EDA ModelSim ngspice Octave Perl Python Software Developer Synopsys Avanwaves Synopsys Cosmos Synopsys Design Compiler Synopsys HSPICE Synopsys NanoSim Synopsys PrimeTime System Verilog System-C Tcl/Tk Verilog VHDL Xilinx ISE

Area of Expertise

Academic: Research Academic: Student Analog: Design Analog: Modeling Analog: Simulation Analog: Verification CAD: Scripting CAD: Tool Development Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Signal Processing design space exploration of VLSI system designs Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Neural Networks RTL code generation SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: Test Programming VLSI layout design

Manikanta

Skills

Perl Tcl/Tk

Area of Expertise

Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Per Magnus Østhus

Synthesis and STA guy

Skills

C/C++ Octave Perl Python System Verilog Tcl/Tk Verilog

Area of Expertise

CAD: Scripting Digital: RTL Digital: Synthesis SoC: Verification

Cagri

Skills

C/C++ Perl Python Software Developer SPICE Opus VHDL

Area of Expertise

Business: Design Services Miscellaneous: Neural Networks SoC: Verification

Prasad Pandit

Skills

C/C++ Eagle CAD Magic CAD Python System Verilog Verilog

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification

Klaus Strohmayer

Independent Digital Design and Verification Expert with more than 20+ years of experience and founder of semify. While working for established semiconductor companies like Infineon, Dialog Semiconductor and NXP I was responsible for bringing ideas into working ASICs. I developed USound’s first ASIC from FPGA based prototyping to tapeout with minimal resourcing, demanding timeline and tight area and power consumption constraints. Currently I'm acting as a consultant for easyIC and Cypress / Infineon. In addition I'm is also lecturer at the FH Joanneum Graz and guest lecturer at the Technical University Graz.

Skills

C/C++ Matlab Python System Verilog Tcl/Tk Verilog

Area of Expertise

Business: Design Services Circuits: Filters Circuits: Microcontrollers Circuits: Sensors Circuits: Signal Processing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: FPGA Programming

Saroj Rout

Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.

Skills

Calibre Eagle CAD Magic CAD Matlab ngspice Octave Perl Python Scilab SKILL Spectre System Verilog Tanner L-Edit Verilog

Area of Expertise

Academic: Teaching Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Design Services CAD: Scripting Circuits: Filters Circuits: Power Management Circuits: Sensors Circuits: Signal Processing Digital: RTL SoC: ESD System: PCB System: Signal Integrity System: Test Equipment System: Test Programming

Bertrand PIGEARD

Hello, I'm an IC Designer Analog/RF with digital skills. I worked mainly on PLL for mobile tranceivers. I used to work on Cadence Design flow for 20 years.

Skills

C/C++ Cadence Virtuoso Calibre Diva Matlab ngspice Octave Perl Python Scilab SKILL Spectre Tcl/Tk Verilog VHDL

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification CAD: Scripting CAD: Tool Development Circuits: Communication Circuits: Memory SoC: Floorplanning

harshitha yadavalli

Skills

Cadence Virtuoso System-C Verilog

Area of Expertise

Academic: Student Analog: Simulation Digital: RTL SoC: ESD

vyas v

Skills

Tcl/Tk

Area of Expertise

SoC: Floorplanning

Srimanth

Skills

Eagle CAD Python Software Developer Verilog

Area of Expertise

SoC: Verification

Mayuresh Rajwadkar

Silicon Entrepreneur with extensive experience in Digital Physical Design, EDA and HPC Infrastructures for Electronic Design.

Skills

Cadence Encounter Cadence Virtuoso Calibre Hercules Leadership Perl Python Spectre Verilog

Area of Expertise

Business: Design Services Business: Sales CAD: Scripting Digital: Placement and Routing Digital: Verification SoC: Floorplanning System: PCB

Nimit Nguansiri

Skills

Cadence Encounter Calibre Hercules Leadership ngspice Tcl/Tk

Area of Expertise

Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Thiago Coura

Skills

Python System Verilog Tcl/Tk Verilog

Area of Expertise

SoC: Verification

Daniel J Wisehart

More than 25 years in FPGA design

Skills

C/C++ Perl Python System Verilog Verilog VHDL

Area of Expertise

Circuits: Communication SoC: Floorplanning System: FPGA Programming

ROSHAN ALI SK

Skills

C/C++ Cadence Virtuoso

Area of Expertise

SoC: ESD SoC: Floorplanning SoC: Verification

Sandipan Sinha

Skills

C/C++ Cadence Virtuoso Matlab Verilog

Area of Expertise

Academic: Student Analog: Design Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning System: Signal Integrity

Chaitanya Parashar

Skills

C/C++ Cadence Virtuoso System Verilog Tcl/Tk Verilog

Area of Expertise

Academic: Student Digital: RTL SoC: Verification

Mehmet Fatih Gülakar

A digital design engineer, interested in memory hierarchies and high speed interfaces.

Skills

C/C++ Cadence Encounter Cadence Virtuoso Matlab Python System Verilog Tcl/Tk VHDL

Area of Expertise

Academic: Research Circuits: Memory Circuits: Microcontrollers Circuits: Power Management Digital: Placement and Routing Digital: RTL Digital: Synthesis Miscellaneous: Cryptography Miscellaneous: Neural Networks SoC: Floorplanning System: Signal Integrity System: Test Programming

Sajal Goyal

Skills

C/C++ Cadence Virtuoso Matlab System Verilog Tcl/Tk Verilog

Area of Expertise

Academic: Student Digital: Placement and Routing Digital: RTL Digital: Synthesis SoC: Floorplanning SoC: Verification

pranay reddy

Skills

C/C++ Cadence Virtuoso System Verilog Verilog

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification SoC: Floorplanning SoC: Verification

Anton Balbekov

Skills

C/C++ Cadence Virtuoso Calibre Leadership Netgen Python SKILL Software Developer Spectre System Verilog Tcl/Tk Verilog

Area of Expertise

Academic: Research Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Business: Patents CAD: Scripting CAD: Tool Development Circuits: Memory Digital: Placement and Routing Digital: Synthesis Digital: Verification SoC: Floorplanning SoC: Verification System: Power Integrity

Florian Ballenegger

Analog and mixed-signal IC designer.

Skills

C/C++ Cadence Virtuoso Calibre Matlab ngspice Python Spectre

Area of Expertise

Analog: Design Analog: Layout Analog: Simulation CAD: Scripting Circuits: Power Management SoC: ESD

Tigran Poghosyan

Skills

Cadence Encounter Cadence Virtuoso Calibre Hercules Python Tcl/Tk

Area of Expertise

Analog: Layout CAD: Scripting CAD: Tool Development Circuits: Memory Digital: Placement and Routing Digital: Synthesis Digital: Verification SoC: Floorplanning SoC: Verification

kowtarapu chaitanya

Skills

C/C++ Cadence Virtuoso System Verilog Verilog ltspice

Area of Expertise

Analog: Design SoC: Verification

Shivam Potdar

RISC-V Enthusiast GSoC 2020 @ FOSSi Foundation RA @ CAD Lab, IISc Bengaluru, India EE Senior @ NITK Mangalore, India

Skills

C/C++ Eagle CAD Matlab ngspice System Verilog Verilog c

Area of Expertise

Academic: Student CAD: Scripting Digital: RTL Miscellaneous: Neural Networks SoC: ESD System: FPGA Programming

Denise Cocco

President and CEO