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Theodoric Xie

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LinkedIn: Public Profile
ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.

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Skills

C/C++ Python Software Developer System Verilog Verilog

Area of Expertise

Academic: Research CAD: Scripting CAD: Tool Development Circuits: Signal Processing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: FPGA Programming

Interests

HLS high-level synthesis chip design computer architecture accelerators research

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