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"profiles" search for "skills": DC

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Number of Results: 13

Caspar van VRoonhoven

>10 years of experience in precision analog and sensor interface IC design.

Skills

C/C++ Cadence Virtuoso Leadership Python SKILL Spectre Verilog Precision Verilog-AMS ADCs Sensors Reference circuits

Area of Expertise

Analog: Design Analog: Layout Analog: Modeling Analog: Simulation Analog: Verification Circuits: Sensors

ardencaple

Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.

Skills

C/C++ Leadership Python Verilog VHDL DC PrimeTime

Area of Expertise

CAD: Scripting Circuits: Filters Circuits: Microcontrollers Circuits: Signal Processing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: Fabrication Process System: FPGA Programming Digital audio IoT Soc Mixed Signal

Ahmed Ramzy

Skills

C/C++ Octave System Verilog Tanner L-Edit Verilog VHDL ICC DC

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis

Roman Gauchi

Roman Gauchi received the M.Sc. in Electrical Engineering from Polytech Grenoble, France in 2017 and the Ph.D. in Electrical Engineering from CEA-LIST, Grenoble, and University of Grenoble Alpes, France in 2021. Dr. Gauchi is a Postdoctoral Research Associate at the University of Utah, since March 2021. His main research interests are emerging technologies and reconfigurable architectures, digital integrated circuit design and embedded software.

Skills

C/C++ DC Python System-C Verilog VHDL

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis System: FPGA Programming

Anand Chaudhary

Skills

Analog Design ADC LDO

Area of Expertise

Analog: Design

Jaehyeok Jang

Skills

ATPG CDC DFT Lint RTL coding Specification Static Timing Analysis Synthesis Simulation

Area of Expertise

Digital Design

VLSI Project

Skills

Electric CAD Verilog adc

Area of Expertise

Academic: Student

Yunus Emre ERYILMAZ

Skills

C/C++ Python Tcl/Tk Verilog Synopsys DC NXT

Area of Expertise

Academic: Research Academic: Student Digital: Placement and Routing

Nikolaos Giannopoulos

Skills

C/C++ Cadence Virtuoso Python System Verilog Tcl/Tk Verilog SDC

Area of Expertise

Academic: Student

Nandhini Jayapandian

Skills

Verilog Synopsys DC Synopsys ICC Synopsys ICC2 RedHawk

Area of Expertise

VLSI

Mohamed Hossam

My name is Mohamed, I'm from Egypt, I'm studying at the electronics and communications engineering department at Cairo University, I'm an undergraduate student and my expected graduation year is 2024. I am interested in digital design track, I have done many projects related to this field. I am very passionate to get this experience and I am sure that I will do great work with you.

Skills

Tcl/Tk Verilog STA Power aware Design PnR DFT CDC Synopsys Design Compilier

Area of Expertise

Academic: Student

Likhit Daggubati

Skills

Perl Python Tcl/Tk Verilog Synopsys DC Synopsys ICC2 Synopsys PT Synopsys StarRC-XT

Area of Expertise

Digital: Synthesis SoC: Floorplanning System: Chip Editing

Mohammed Salah

Experienced ASIC Digital Design and Physical Implementation Enthusiast

Skills

Cadence Encounter Tcl/Tk Verilog Synopsys Design compiler (DC) Synopsys Formality Synopsys ICC Synopsys ICC II Synopsys PrimeTime QuestaSim Vivado

Area of Expertise

Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis