Trained as a Software Engineer, i am an advocate for Libre Ethical Technology in business.
Hi! It's good to see you being here, good to believe we have same interests. Coffee Design Debug Improve OpenSource
Silicon Design Engineer
I m the Account manager, at Adroitec Systems Pvt Ltd, we are providing physical design services
Linkedin - https://www.linkedin.com/in/bhawandeep-singh-1b164517/ PhD student in CSE department in UCSC, advised by Prof. Jose Renau. My areas of majors are CPU design, digital design and embedded software.
An independent and self-motivated fpga engineer with many product and service based project in semiconductor and cryptography market. More than three years of experience in the crypto mining market. Involved in product design/development, management.
Teacher/researcher at the Electronics Department (DEEC) of Universidad Nacional de Tucumán, Argentina
Digital designer and embedded software developer. Experience from telecom and computer vision.
20+ Years of Experience in Chip Design
I have been working on Analog/Mixed-Signal Integrated Circuits design since last 16 years. I graduated from NED UET, Karachi in 2001 and then worked with Avaz Networks, a Silicon-Valley Company on RTL design and verification of a high-density Line Echo Cancellation Engine for a couple of years. Joined Linkoping University, Sweden in 2003 for Masters in SOC, which concluded with a Masters Thesis on Sigma-Delta Modulators with Fraunhofer Institute of Integrated Circuits, Germany in 2005. The same year I joined University of Trento and Fondazione Bruno Kessler, Trento, Italy for my PhD on Readout Interface Design for MEMS Capacitive Microphones. Worked with ST-Microelectronics, Milano and Analog-Devices, Copenhagen as a Guest PhD Student. This Phd results in 20+ publications and 2 patents with 3 successful MEMS Readout ASICs.
Author of Yosys, IceStorm, PicoRV32, and other Open Source things
Developer of open source EDA tools on Open Circuit Design
VLSI circuit design engineer with significant experience in microprocessor design in semiconductor processes from 65nm to 10nm. Provided register file designs and design training for Intel Big Core and SOC projects. Helped create semi-automated array layout methodology. Established cross-organizational methodology for variation analysis in register files. Converged memory IP handling across multiple organizations.
Engineer, who typically worked in start up environment. So do A-Z, a-z and 1 - infinity if something has to work
I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.
I am an Analog/mixed signal IC designer. I worked with different technologies like ams035, xh035 and st 130nm.
Recent college graduate from San Jose State University with Masters in Electrical Engineering degree. Specialization - Digital Design and Verification.
I am a digital design/verification engineer. I have 2 years of full-time industry experience. In total, I have 4.5 years of experience in RTL design, Electronic Design Automation and Verification using VHDL/Verilog, Perl, Tcl and Linux. I was the #1 graduate of Bahcesehir University in Mechatronics Engineering in 2013
I'm VLSI Design Engineer aspirant and like to work on design challenges in VLSI domain. I like to keep updated of cutting-edge technology in my field of interest.
I'm a DFT Engineer, i would like explore the world of semiconductor technology
Mad about OSS system design, specialized in video compression and image processing, CNN and dedicated HPC architectures. New deals in low power design
A student pursuing B.Tech in Electronics and Communication branch.
HW development engineer
I am Ashwini ,done Masters in Electronics. Very much interested to learn VLSI Physical Design
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,
IC Design Engineer
Master's student at UFCG. Work with Cadence tools. I work with AMS and digital circuits (using Verilog language) and analog layout as well.
I am Electronic Engineer from Chile, I like DSP and radioastronomy applications an ordinary guy
Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.
i am currently persuing mtech from in vlsi design from DTU india.
Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.
VLSI design project manager
I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.
Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.
Hardware design engineer
Learner for life
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
I am researcher with goals of developing high end technologies for the future.
4+ years of VLSI Backend experience. Working as Physical Design Engineer. Expertise in Analog layouts, physical verification and Physical Design. Open to learn and explore other domains of VLSI design.
Teaching assistant for ASIC/FPGA and digital ICs courses.
Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.
Graduated with a Micro-electronics Master from Bordeaux university, France, I have now 18 years of experience. Worked in France, England, Belgium and Brazil, within 5 companies. Implemented physical design flows, recruited, trained and supervised trainees to experienced engineers, I have a vast experience in setting up complete flow (2 companies were startups), as well as signing off important design within NXP and CSR, all to successful first time right silicons. Able to work in total independence as well as within a team, I consider myself as optimist, result focused, with attention to detail while keeping a good trade between time to market and risk taking.
Lecturer UiTM
Physical Design Engineer
Associate Professor (Electrical and Electronic Engineering) Implantable chip design Low power sensors
Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.
Physical Design Engineer
Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)
Physical design engineer
Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.
Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.
An experimental physicist through sensor and instrumentation development.
Umer Imran is eager to work in the field of Computer Architecture and Memory Consistency. He is currently working as a Design Verification Engineer at Lampro Mellon, a training firm with the vision to transform Pakistan’s talent pool into leaders of RISC-V based SoC design. He constantly aims to gain expertise in the various domains of SoC Design including IP Design, ASICs, and low power architectures.
Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design. Fiction writer (National Literature Award for Novel, 2011, Costa Rica)
A young and ambitious individual, eager to apply my knowledge of Computer Architecture and VLSI Physical Design to develop hardware that is performance, power and area efficient, while actively contributing to the development and growth of the open-source semi-conductor industry
Expert in embedded and mobile applications since 2003. Has many years of experience in software and hardware development, effective team management. Excellent in the research and development, technology findings and implementations.
Mad Scientist
Managing Partner
Physical Design Engineer
Interested in Design, Verification, and Hand-off of Analog IPs. Worked on the definition, modeling, design, verification of DC-DC converters, Chargers, Ideal-Diodes, LDOs, Regulators, Bandgap references, Current limiting and sensing architectures. Excited for challenges in Analog Design, Layout and Post-silicon verification.
Physical Design Engineer
Eduardo is an Electrical Engineer engaged in hardware development with a true passion for developing and enhancing applications. While at university, he worked in a variety of projects, from VHDL in a SOC project, to a PCB for a power circuit, and even web interfaces for electronic devices network connected. He allies his technical background with great communication skills. He is used to and is passionate about working in diverse cultural environment as was his period as an international student in Japan. He also got a certification in in Digital Integrated Circuit Design and Project Flow with Cadence tools (IC Brazil Program). Currently he works at HT Micron, and is interested in positions related to chip design, hardware design, embedded software development and similar areas.
A recent graduate student from Syracuse University major in Electrical Engineering with focus in VLSI Designs
Principal Engineer at ONiO AS
Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.
MSC in Electrical Engineering BSC in Electronics Two patents in mathematical software in Engineering design and digital signal processing utility box Undergo private research for commercial use in the areas of very high frequency analog and digital circuits
ASIC Developer at Ericsson, trying hands with the open source tool flow.
I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.
ASIC architect and designer. Specialize in deep learning, video, image and signal processing, and compression. Professor of Electrical and Computer Engineering at The College of New Jersey.
Research Scholar | Analog Circuits | EMI Immune Amplifiers | Neuromorphic Circuits
I am research asistant at TOBB Economy and Technology University
Assistant Professor (IISc) | Ph.D. & S.M. (MIT) | B.Tech. (IIT-KGP)
I'm an engineer with both software and hardware background. I'm building next generation distributed storage system.
I am Physical Designe Engineer -1 at Signoff Semiconductors
I am a Master's student who has to know for learning and do experiments as well as for writing technical blogger. My website links are given below to connect with my open-source family of the VLSI champions. https://nishitnathwani.blogspot.com/ https://geniusvlsi.blogspot.com/
Still an entry-level electronic engineer. Absorbing and practising information and knowledge. Just for curiosity and fun.
Pursuing masters in VLSI at IIT INDORE.
I am interested in the platform-based complete SoC design/verification automation methodology and framework
I am an Assistant Professor in Electronics Dept. UET Taxila, Pakistan. I did my PhD from VLSI Lab Politecnico di Torino, Italy. My research interests are digital hardware implementation of Communication and DSP algorithms.
I have been delving into the IC design industry for the last 3 years. I started with circuit designing on Virtuoso and am now working with the APR flow for the last 1.5 year
I am working as Co-founder & CTO of Upplysning Robotics, which is focused on the development of biomedical devices like digital stethoscopes with built-in ECG and PCG, auto-detect heart irregular arrhythmias, and its flagship project is the design of artificial hearts and implants inside the human body and also Cardiac Robotics medicals devices
current Phd Student in UCSC Hardware System Collective group formerly worked in Qualcomm Wireless R&D team as a design verification engineer
Professor of CSE at UC Santa Cruz
Roman Gauchi received the M.Sc. in Electrical Engineering from Polytech Grenoble, France in 2017 and the Ph.D. in Electrical Engineering from CEA-LIST, Grenoble, and University of Grenoble Alpes, France in 2021. Dr. Gauchi is a Postdoctoral Research Associate at the University of Utah, since March 2021. His main research interests are emerging technologies and reconfigurable architectures, digital integrated circuit design and embedded software.
Collaborative development of open source technologies for public health.
Principal engineer leading PNT product development at GE Aerospace
I love electronic systems. I am interested to learn all about electronic systems.
I am an Associate Professor teaching VLSI design, hardware security, and digital circuit design at Drexel University. My research interests include analysis, modeling, and design methodologies for high performance digital and mixed-signal integrated circuits, power management for SoC and microprocessor circuits, hardware security, including digital and analog obfuscation and Trojan detection, and electric and thermal modeling and characterization, signal and power integrity, and power and clock delivery for heterogeneous 2-D and 3-D circuits.
A researcher and VLSI guy
Kashif Inayat currently working as a doctorate fellow researcher at System-on-Chips (SoC) Laboratory, Electronics Engineering Department of Incheon National University, South Korea. He considers himself fortunate to have the opportunity to work under Prof. Jaeyong Chung at Incheon National University. Prior to starting his Ph.D., he completed his Master of Science in Electronics and Computer Engineering (ECE) from graduate school, Hongik University in 2019 under the supervision of Prof. Seong Oun Hwang. Moreover, during MS studies he worked at Information Security and Machine Learning Lab, Hongik University, South Korea as a graduate researcher for 2.5 years. Furthermore, he chaired the special sessions at International Conference on Green and Human Information Technology (ICGHIT 2019), held in Kuala Lumpur, Malaysia (Jan, 16-18, 2019). Moreover, he is a registered member of the Pakistan Engineering Council and a reviewer for the IEEE Access Journal.
I am VLSI Trainee wanted to design chips
Postgraduate student at IIT INDORE
I have been delving into the IC design industry for the last 3 years. I started with circuit designing on Virtuoso and am now working with the APR flow for the last 1.5 year
I have been delving into the IC design industry for the last 3 years. I started with circuit designing on Virtuoso and am now working with the APR flow for the last 1 year
Digital design engineer Msc Student at cairo university Faculty of Engineering
Doctoral student at the Tokyo Institute of Technology.
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
Experienced SW developer (C/C++/C#) and digital HW designer (SoC/FPGA)
I am a fourth year Electrical engineering student interested in design and verification of digital and analog integrated circuits. - I have experience doing layout for RFIC using SOI processes where I gained extensive knowledge in device physics, floorplanning, ESD protection techniques, and techniques to mitigate manufacturing limitations -I have extensive experience using Cadence Virtuoso layout XL , running verification simulations using Cadence ADE Explorer, EMX, and PEX.
Currently working as a Graduate Instructor in the department of Electrical and Computer Engineering and pursuing my Ph.D. in Electrical Engineering at the University of Missouri-Columbia. My research focuses on the development and design of low power decision-making Integrated Circuit (IC) using different type of Ai/Machine-Learning techniques. Besides researching on developing future technology, I'm also a professionally trained Vocalist in traditional South-Asian music majoring in Tagore and have experience in freelancing of 5 years in Digital Art and Graphics.
Iam an Under-graduate currently pursuing B.Tech 3rd year in Electronics and Communication Engineering at Rajiv Gandhi University of Knowledge and Technologies, campus in Nuzvid, Andhra Pradesh 521201
I am a VLSI enthusiast looking for an opportunity to make my career as a Design engineer in the Hardware Industry.
PhD student working on a superconducting FPGA design aiming to work on neuromorphic computing in the future.
working as Assistant Professor in Sree Vidyanikethan engineering college, Tirupati.
Broad background in ASIC's with expertise spanning networking, high speed compute and digital signal processing. Expertise across all areas of development from verification to tape-out.
My name is "YERRA BHASKARA VARA PRASAD" pursuing B.tech ECE 3rd year in Rajiv Gandhi University of Technologies, Nuzvid, Andhra Pradesh 521201.
I'm Harsha,I'm pursuing my undergraduate in the domain of Electronics and Communication Engineering from SRM University AP.
open source autopilot guy
Beginner Digital Designer
SoC Architect.Technologist. Hands-on experience in complex low power SoC designs, from concept to production. Excellent track record in successful development and production of ASICs, Technologies: Bluetooth, WLAN, IoT, Gigabit Ethernet, EPON networks, Interface ICs, Broadcast TV and Communication controllers. Demonstrated consistent track record of first-pass silicon success. PhD in Low power VLSI. Recipient of US and Indian patents. Core Competency: Chip Architecture, Micro Architecture, logic design, RTL Verilog coding, Chip level verification, Static Timing analysis, Formal Verification, design rule checking, AXI, AHB and APB bus protocols, Digital ASIC methodology, DFT methodology, Low Power ASIC design, Interfacing with backend teams, Timing closure, Post silicon bring up and validation, Project Planning, Scheduling and Management, FPGA Prototyping. Author of Book "A Practical Approach to VLSI System on Chip (SoC) Design" published by Springer Nature. Domain experience: Communications, EPON, WLAN, Bluetooth, IoT, Healthcare, Nextgen TV, Automotive. Managed dynamic, cross cultural teams of size 40 to 100. Standards worked on IEEE802.3, IEEE802.11b, ac, ad. ATSE 3.0, Automotive ethernet, Bluetooth Quality standards: ISO 9002, ISO 13485, IEC 60601-2 Funded Research: Derivative Low power standard cell library development PhD Guidance: 2 one in Asynchronous VLSI design methodology and second in Sub 1V power supply for complex SoCs. Co-founded healthcare company:Sensesemi Technologies Pvt. Ltd. Academic research head and taught engineering students for their undergrad, Post grad and PhD courses Chair, IEEE NanoTechnology Council, Bangalore Section as a founder Chairperson, Current Senior IEEE member.
I am a PhD student at National University of Sciences and Technology, Islamabad
I am professor at Dept of EEE, BUET, Passionate to teach students IC Design and Fabrication Skill.
Hardware Systems Architect at AroLeap
Hardware Design Engineer with 7 years of experience in RTL/SoC/FPGA Design, Integration, and Verification. Proficient in Front End Design tools and methodologies. Passionate about IC Design/Fabrication, AI, and IoT prototyping.
My area of interest is Analog and Mixed signal circuit design. I teach Electronic Circuit, VLSI design and Signals & Systems for under graduate students and Analog Integrated Circuit Design, Data Converters and Clock & power management circuit courses for Masters students. I also teach VLSI lab courses for both both undergraduate and masters students. Every year I supervise both undergraduate and masters students in analog circuit design projects. Presently I am involved in SRC project as Co-task leader in Analog and Mixed Signal circuit verification project using Machine learning techniques.
Digital and Mixed Signal Verification Engineer, with 9+ years of industry experience, looking to explore the entire chip design cycle.
Master's research student in IC design has hands-on experience on Cadence tools like Virtuoso, Genus, Innovus, Calibre. Motivated to learn more in the field of IC design
I'm currently working as an Optics Design Engineer for Biotech applications. My main interests are (Micro/Opto)Electronics, Optics and Photonics, Data Science and Embedded Systems.
I`m a digital IC designer working for a RISC-V company RIVAI in China, which has close ties with RIOS Lab.
I am a Senior Undergraduate in Electrical Engineering Department at IIT Gandhinagar, India. VLSI Design and the ability to tweak at the hardware level interest me a lot!
Cryptography and security researcher at Seagate Technology
VLSI Professional with 2.3 years of experience and adequate knowledge in RTL Design, UPF, SDC, Lint, CDC, Synthesis, Physical Design, STA and Scripting. I love Computers and I am interested in RISC V
abyssal witch | deranged catgirl hardware/software engineer + vtuber | that crazy SCSI girl | she/her
ASIC and FPGA design and verification Engineer with a sideline in bring devops to Hardware projects
Test Engineer
I am a microelectronic engineer/CMOS designer with an emphasis on digital & low-power electronics and front-end circuitry. I am an academic at The University of Sydney, Australia and working on devices to data solutions for a range of problems such as unmet needs in electronic monitoring/sensing and interventions in neurological disorders.
Assistant Professor. ECE. University of Pittsburgh. Interests: Neuromorphic and Biomedical Systems Design
Fresher interested in asic physical design and looking for job opportunities in physical design engineering
I am a student in my final year of B.tech in electronics. I am eager to learn about vlsi and its technology. I want to take part in openMPW program
Just another big dreaming engineer with a desire to learn silicon microfab
Received B.S. degree from Electrical and Electronics Engineering in Middle East Technical University, Turkey, in 2019. Currently, pursuing M.S. degree from Electronics Engineering in Bogazici University, Turkey. Research interests are computer architecture, hardware security and secure memory architecture
13+yr ASIC Digital Designer. Master degree on Microeletronic Sensors. Worked on NXP through different projects on automotive and consumer/general market MCUs on areas from SoC Integration to Timing Sign-Off
Digital System Designer.
Semiconductor professional with 12+ year experience in ASIC hardware design and methodology development. Main expertise is in chip STA signoff - top level, IO timing, High speed design timing, and good knowledge of RTL design, Physical design (Layout, CTS, Route, DRCs), Synthesis and Formal Verification. Have also completed business management studies and looking for interesting opportunities in chip product development and management.
Chip Design CAD Expert
Physical Design over 10 years, Front-End Design over 4 years, have knowledge on DFT, STA, ...
I am the founder of Aurifex Labs LLC. I have a degree in EE and have a strong interest in computer architecture, but have been a software developer/entrepreneur professionally. I also have a little audio DSP background. I created Prospero.Live, a collaborative software development platform.
I am the founder of Aurifex Labs LLC. I have a BSEE from Wilkes University. I've spent most of my time in software, education, and entrepreneurship, but have spent the past year learning VLSI and am excited for this new era of open source hardware/tools.
Senior software engineer in Tron Future Tech. My work is related to CPU/FPGA heterogeneous computing for radar signal processing. Capable of designing RTL IP, implementing Linux kernel driver and system software programming.
I waiting for my Blå (E.A.) & untill this no ©omment
Computer Engineering Student and hardware design enthusiast. Enjoys programming and soldering.
I am interested in new things. I've designed chips from definition to polygons, mostly in the pursuit of new capabilities.
Electronics Engineer. Design Embedded Systems , Firmware professionally and fiddle with others :)
A master's student studying the design of electronic devices
Physical Design Engineer at Laksh Semiconductors
Dad. Partner. Scientist. Activist. Maker. — He/Him
I am a PhD. Telecommunication Engineer with 25 years of working experience in the industry. I started my career in 1997 as an IC Design Engineer, then I moved to other technical and management roles in the semiconductor and aerospace industries. Since 2017 I am also teaching IC Design at University for MsC. graduate students.
I am an Electronics Engineer now continuing my MS in electronics from COMSATS Abbottabad in Analogue Chip Design.
Final year student of Electrical Engineering at UET Lahore. Area of expertise is Digital Design, Computer Architecture and SOCs.
ASIC Verification Engineer with 12+ yrs of exp.
IC design Engineer
Assistant Professor in the Department of Electrical and Computer Engineering at The University of Mississippi
Electrical Engineering student at UFMG, scheduled to graduate in Dec/2022. Experience in the automotive sector by the Formula Tesla UFMG team, designing electrical and electronic systems. Exchange experience in South Africa for 3 months studying English and working voluntarily in needy settlements. Currently, work as Software Engineer at Cadence Design Systems.
I am an Assistant Professor in the Electrical Engineering Department. My research activities are in Neuromorphic Computing and Engineering and span from the development of efficient models of computation to novel microelectronic architectures, with CMOS and emerging technologies, for both efficient deep learning and brain-inspired algorithms. My long-term research goal is to understand the principles of computation in natural neural systems and apply those for the development of a new generation of energy-efficient sensing and computing technologies. My research outputs find use in several application domains as robotics, machine vision, temporal signal processing, and biomedical signal analysis.
Hon-Piu Lam, is a Ph.D. candidate in the Department of Electronic and Computer Engineering of the Hong Kong University of Science and Technology (HKUST). He was an analog IC designer engineer in Valence Semiconductor from 2004 to 2007. From 2007 to 2015, he joined Fujitsu Semiconductor focusing on the embedded NOR flash design. He has been a researcher in HKUST focusing on the integrated power electronic and data converter. His research interests include readout electronics, integrated power electronics and radiation hardened electronics for experimental physics.
IC Designer
A graduating IC design student with lots of passion and interest for electronics design!
MS Electrical Engineering Fellow with a focus on Integrated Circuits and Systems Design. Skilled in Cadence (Virtuoso, Innovus and Genus)
Graduate student passionate about integrated circuit design for biomedical applications
D Gracia Nirmala Rani received the B.E. degree in Electronics and Communication Engineering from Syed Ammal Engg College, Madurai, India, in 2004, and M.E. degree in VLSI Design from Karunya University, Coimbatore, India in 2007. She has awarded Ph.D. degree in VLSI Design from Anna University, Chennai India in 2014. She is working as an Associate Professor in Thiagarajar College of Engineering, Madurai since 2007. She teaches courses on system/digital and analog electronic design and VLSI processor architectures. Currently, five research scholars are doing their research under her guidance. She has authored or co-authored 42 international journal and conference papers like IET Circuits, Systems and Devices, Spinger, Wiley and Elsevier Publications. Also she has published 3 Books/Book Chapter in Springer LNCS and CCIS Publications. She has filed 2 Patent in BioMedical Engineering Field. She has guided the B.E students’ project which won the India Cadence Design Contest Award 2017 and 2018 instituted by Cadence Design System Pvt Ltd, Bangalore. In 2018, she was the technical program chair of the 22nd International Symposium on VLSI Design and Test. She is serving as a reviewer in IEEE Transaction on Nanotechnology, Elsevier and Inderscience Journals, respectively. Her research interests include RFIC Design, Physical Design Automation, Optimization Algorithms using Machine learning for IC and mixed signal circuits and systems for Bio-medical Devices.
I am a Masters fellow student of RFCS2 Lab in IC Designing.
Automation enthusiast (likes to code in Perl). At this time, Doing Master's in VLSI Design and working as an intern @intel. Great learning experience doing both simultaneously. Have experience designing in both circuit (Low power & timing) & device level (high performance designs for digital applications). Obtained honor of 3rd position in concept design competition by ISRO for designing temperature & radiation resistant Tunnel FET. Would love to work with all device technology enthusiasts as opportunities arise.
Trying never to sit back and enjoy but to come forward and prove myself
I am en Electronics Engineer currently Pursuing my Masters in IC design from FAST NUCES Islamabad.
Post-doctoral research fellow in the discipline of Software and Systems, School of Computer Science and Statistics, Trinity College Dublin, with a keen interest in learning new things, specially related to computer science and engineering. Around 4 years experience of teaching and research and more than 10 years of experience in architecture design, optimization, analysis, implementation and verification of digital and digital signal processing systems on FPGAs and ASICs. Diversifying research career by working on quantization of deep convolution neural networks. Author of three peer reviewed journal publications and five international conference publications.
electronic system designer / software and hardware engineer, embeded system expert, signal expert, proccess designer, researcher, Developer of complexity and reversal wantings. Reverse engineer. i addopt my whole life to this science. thank you for presentings of quantum, psych
I have done electronic engineering from University of Engineering and Technology Peshawar in 2021, currently, i am doing MS in Electrical Engineering (Specialization in IC Design) from National University of Computer and Emerging Science(FAST-NUCES).
Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.
Mixed-signal designer
Innovative developer with recognized success at designing, testing, implementing and maintaining computer hardware and software. Critical thinking and forward-focused professional coding in various programming languages. Delivers clear and engaging communications to colleagues and customers and inspires enthusiasm for engineered products and systems.
I'm a new grad Digital Design engineer working. Looking forward to contribute to open source silicon projects.
MS in IC Design Fellow, RFCS2 lab at FAST-NU Islamabad, Pakistan
Independent Digital Design and Verification Expert with more than 20+ years of experience and founder of semify. While working for established semiconductor companies like Infineon, Dialog Semiconductor and NXP I was responsible for bringing ideas into working ASICs. I developed USound’s first ASIC from FPGA based prototyping to tapeout with minimal resourcing, demanding timeline and tight area and power consumption constraints. Currently I'm acting as a consultant for easyIC and Cypress / Infineon. In addition I'm is also lecturer at the FH Joanneum Graz and guest lecturer at the Technical University Graz.
Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.
Silicon Entrepreneur with extensive experience in Digital Physical Design, EDA and HPC Infrastructures for Electronic Design.
U.G. Student at IIT Gandhinagar.
A digital design engineer, interested in memory hierarchies and high speed interfaces.
Hello I am Rakesh , I am pursuing my Under Graduation in Electronics and Communication Engineering at KLE Technological University, Hubballi. I am looking ahead work in Digital VLSI Domain. :D
RISC-V Enthusiast GSoC 2020 @ FOSSi Foundation RA @ CAD Lab, IISc Bengaluru, India EE Senior @ NITK Mangalore, India
Electronic engineer and science communicator.
I’m an engineer always looking to learn, optimize and automate. I work on data analytics to provide deep insights into hardware designs, particularly physical design flow. Exploring areas to facilitate design engineers in taking data driven decisions for faster design turnaround times. I like to think about life. I like experimenting with different techniques (using software tools and meditation) to optimize my day and work effectively. In my free time, I’m learning Web Programming to build my own blog. I know there are templates and websites but where’s the fun and learning if you don’t do it from scratch? I like mentoring students on how to approach career and life in general.
President and CEO
I am passionate VLSI trainee looking to explore my skills and build few projects which enhance my coding and debugging skills.
R&D Engineer
An analog mixed-signal circuit designer for low-power precision sensor interfaces. See https://staff.aist.go.jp/ippei.akita/
IP, SOC RTL Design engineer, Microarchitecture. Knowledge of Front End
We are group of experienced engineers working in Front-End Digital Logic Design.
Dad. Partner. Scientist. Activist. Maker. — He/His
I am recently completed my post-graduation in VLSI and Embedded system from coep pune(India). I like to work in a backend design of VLSI.
I am Pratika Tripathi. I am in my final year of Btech. I am very interested in physical designing of IC. I had even taken 3 courses of kunal ghosh sir on physical design, stay, and cts. I am doing my final year project in physical design.
For most of my career, I was a CAD technology innovator and CAD system architect at Intel Corporation. I signed up recently for a Udemy class called "VSD - Making the Raven Chip: How to Design a RISC-V SoC." The class pointed me to Efabless.
Ph.D. in electrical engineering, 25 years experience in mixed-signal IC design
A fresh graduate interested in chip designing, learning new things everyday!
SubIP and SoC Design Verification Engineer. Extends to running Full Chip Emulation on Palladium and Protium Platforms.
Amel is an Digital IC designer interested , used to work on HDL based Design for testability, Formal verification of Semi custom and IP based SOC DFT. Currently, working on IC design for Reliability. She designed a Test structures chip for Bias Temperature Instability characterization and analysis using TSMC 180nm Technology.
Research Associate at Micro Electronics Research Lab (MERL) working as a hardware design engineer.
I'm a PhD student working to make mixed-signal chip design more accessible, drawing inspiration from software development techniques. Prior to starting the PhD program, I spent a number of years working in industry at both the chip- and PCB-level on optical sensors and power systems.
I am currently working as a Research Associate. We are doing research and development on RISC-V Technology.
PhD Student, School of Electrical and Computer Engineering, Purdue University, USA. Research interests include Mixed Signal Circuits, High Speed Circuits and Digital System Design
My name is Joel Sanchez Moreno I graduated as a Computer engineer and I currently work as a full time RTL design engineer for a start up. In addition, I am doing a part-time master on High Performance Computing on the Universitat Politècnica de Catalunya (UPC)
Hi, I'm an Electrical & Computer Engineering + Computer Science student at Oregon State University.
I'm a Senior Researcher at the Barcelona Supercomputing Center and Junior Faculty at Polytechnic University of Catalonia (UPC). I'm the recipient of the RISC-V Educator of the Year Award 2019, for the advanced graduate course Processor Design I'm teaching at UPC, which is focused on the design of high-performance safety-critical systems. I'm the PI of the GPU4S project funded by the European Space Agency (ESA) in which we are investigating the applicability of embedded GPUs in space.
Digital Systems and Software Engineer (formerly in management VP and Director of engineering).
PhD Student @ UC Berkeley, formerly SWE @ Google
Research Associate at MERL mainly focusing of firmware and driver development for SoCs.
I am a final year B.Tech undergrad from India highly passionate about digital system design.
I am accomplished digital design engineer having 8 years of industrial expertise . I am currently working on IP design and IP integrations stuffs .
ASIC/FPGA Design Engineer | Former Intern in CERN | Former Cultural Ambassador of Pakistan in USA | Gold Medalist
Electrical Engineer interested in the design of mixed signal ASICs
I hold a Doctoral Degree in ‘Information and Communication Engineering,’ with 22+ years of experience in engineering education in various capacities. I have more than 30 research articles, presented and published in various National, International Journals and Conferences. My research interests are in the following domains and are not confined to VLSI, AIoT, Intelligent Transportation for Smart Cities in India, FPGA-based System Design, etc. My professional membership includes a Fellow, in the Institution of Engineers (India), a Fellow in the Institute of Electronics and Telecommunication Engineers, a Senior Member of IEEE, and a member of ISTE & ACM.
Osaze Shears is passionate about many engineering and computational concepts. These include embedded systems, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and microprocessor technologies. Osaze spends his free time tutoring other students who are interested in learning to become better computer scientists and engineers to benefit the greater society. Osaze is currently a PhD student at Virginia Tech conducting research under the Multifunctional Integrated Circuits and Systems (MICS) lab. His research interests include: • Spiking Neural Networks • Hardware Acceleration • SoC Design with ASICs and FPGAs • Deep Learning • Edge Computing
Enthusiastic VLSI Design Engineer currently working in Domain Specific Architectures
ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.
I am an enthusiastic proponent of open source hardware. See my position paper on the topic: https://ieeexplore.ieee.org/document/7945172.
Adroitec Systems is design Services Company for the VLSI and Embedded Software. Founded in 2017, Adroitec Systems is having Register Office at Visakhapatnam with branch offices in Bangalore. Adroitec Systems delivers cutting edge solutions across a diverse portfolio of services including Physical Design, Physical Verification, and Design Verification. With about 50 highly qualified employees.
Designer specialized on VLSI radiation tolerant architectures and circuits
I've done everything from silicon design at the "bottom of the stack" to System Architecture and Design (with plenty of SW to go with it; at every level)
I'm the CEO of a fabless semiconductor start-up company and have more than 15 years experience in designing mixed-signal ASICs on various foundry processes.
Engineer / VP
Hardware System Designer from ASIC chip to board to SOC platform
I am a senior ASIC and IP development person. My strength is in building high performance ASIC teams that deliver high quality ASIC and IP products .
A software developer, technology manager, and hardware tinkerer aspiring to imbue slices of crystals with intelligence.
We are an open-source research group dedicated to developing cutting-edge RISC-V architectures for integrated systems. Our focus is on IC design and the development of soft IPs, SoCs, and ASICs for both general-purpose and low-power applications. Our team is committed to advancing the field of VLSI design through innovative research and practical solutions.
I am a current Master's student in IC (Integrated Circuit) and Systems Design, as well as a Research Assistant at the Micro Nanoelectronics (MiNE) Lab located at SEECS NUST. I completed my Bachelor's degree in Electronics Engineering from UET Peshawar. As a member of the MiNE Lab team, I am involved in cutting-edge research in the field of micro and nanoelectronics, with a specific focus on the design and development of integrated circuits and systems. My academic and research background has provided me with a strong foundation in electronics engineering, and I am passionate about utilizing my skills to contribute to the development of innovative technologies in this field.
Undergraduate student at Gebze Technical University, Turkiye. Works on custom instructions on Risc-v cores and Risc-v arthitechture.
I'm an ASIC Design Engineer with a focus on SoC verification. With over three years of experience in the field, I have had the privilege of successfully completing and taping out three projects. My expertise lies in ensuring the functionality and performance of complex System-on-Chip designs through thorough verification methodologies. Throughout my career, I have gained a deep understanding of the entire design flow, from specification and architectural exploration to RTL coding and verification. I am proficient in industry-standard verification languages and methodologies, such as SystemVerilog and UVM.
Graduate student in MIT EECS trying to combine stochastic MTJ devices to silicon
Hi! I'm a senior student at the National University of Sciences and Technolog (NUST), and majoring in Electrical Engineering. My focus is Digital Design and FPGA fabrics.
i am a vlsi enthusiast
Associate professor of Microelectronics at University of Cagliari, Italy
I have over thirty years of experience in the semiconductor industry, having worked in fab, EDA and design engineering. have built and led large, geographically distributed teams at a senior manager level. I am passionate about developing talent and skills, particularly in young people from socio-economically underprivileged backgrounds.
An aspiring young electrical engineering student from Pakistan trying to learn and build my expertise in the FPGA/SoC development world with Xilinx Zynq platforms. Working on a machine learning accelerator on Digilent Cora Z7 (Zynq 7000 series SoC) board for my senior year project.
I am a faculty in the department of Electronics and Communication Engineering, National Institute of Technology Arunachal Pradesh, India. Besides, I am associated with the Special Man Power Development Program in the department to undergo research in VLSI. My interests include temperature sensors and SerDes design. I am familiar with Cadence Virtuoso and vigorously monitoring students working in the said areas.
Berna Örs Yalçın received the Electronics & Communication Engineering degree and the MSc degree in 1995 and 1998, respectively, both from the Istanbul Technical University (ITU), Turkey. She received the Electrical Engineering degree in applied sciences from the Katholieke Universiteit Leuven, Belgium, in 2005. Currently, she is a Professor at ITU. Her main research interests include cryptography, embedded systems, and side-channel attacks.
Sr. Electrical Engineer with 40 years of experience, doing R&D, circuit design from concept through layout and to production in Aerospace, Automotive, Industrial and Gas and Oil down-hole business sectors.
30+ years industry experience in hardware and SOC design, with specialisation in Functional Verification, Silicon Validation, SI/PI and Board design
Analog-RF IC circuit and system design engineer.
Hello, my name is Usama Ishfaq. I am an electronics engineer with expertise in IC design. With years of experience in the industry, I have developed a strong understanding of the complexities involved in designing and developing integrated circuits. My passion for electronics and technology has driven me to constantly learn and innovate, ensuring that I stay up-to-date with the latest advancements in the field. I take pride in my ability to work collaboratively with teams and clients to deliver high-quality solutions that meet their specific needs. Thank you for taking the time to read my introduction.
I am a results-driven Electrical Engineer with a strong foundation in digital design, RTL to GDSII flow, and system-level architecture, complemented by hands-on experience with FPGA and ASIC environments. With expertise in Verilog, SystemVerilog, and VHDL, I have designed and implemented advanced digital systems, including high-efficiency MLP architectures and custom ASIC designs for optimized performance and power efficiency
RTL design engineer with experience developing mobile GPUs (Samsung), high-end networking ASICs (Juniper) and CPU cores (MIPS). Co-author of lab manuals and online courses on FPGA design, RTL2GDSII flow and computer architecture. Founder of Verilog Meetup, a Silicon Valley and online community that develops open-source SystemVerilog examples targeting three niches: beginners, students who want to prepare for microarchitectural job interviews and university professors who want to avoid FPGA vendor lock (our examples are interoperable between Xilinx, Altera, Gowin and Lattice and compatible with ASIC flows, such as TinyTapeout and eFabless (in progress)).
Computer Engineering Student at the University of Notre Dame who is interested in AI and Chip Design
To obtain a challenging position as a VLSI Engineer in a reputable organization where I can utilize my skills and knowledge to contribute to the growth of the organization while also enhancing my own personal and professional development.
Graduated as electronic engineer in '93. Think it could be nice and fun to try out this part of the electronic life/world :). I have worked a lot with digital designs over the years, everything from small LED controllers to larger computer boards. And then I am a PCB geek.
FPGA/HW engineer
Senior Computer Science Student at the University of Notre Dame.
Product design and development
VLSI DOMAIN SKILLS --------------------------- • Digital Electronics • HDL: Verilog • HVL: System Verilog • TB Methodology: UVM • Protocols: APB, UART, I2C, SPI • EDA Tools: Modelsim, Quartus Prime, Questasim. VLSI RTL SKILLS ---------------------- • Digital Skills : Combinational and Sequential circuits • FSM • Memories • Verilog : Data types • Operators • BA and NBA • Delays in Verilog • Begin-end and fork-join Blocks • System tasks and Function • Compiler directive • FSM Coding. VLSI VERIFICATION SKILLS ------------------------------------ • System Verilog HVL: Data Types • Memories • Interface • OOPS • Constraint Randomization • Threads • Functional coverage • CRCDV • SV Testbench (Hands on SV Testbench) • Universal Verification Methodology: UVM Objects and Components • UVM Factory • UVM Phases • UVM Configuration • TLM • Virtual Sequence and Sequencer • UVM Testbench (Hands on UVM Testbench).
I am a professional in the field of Chip Design, Primary working on Synthesis, Physical Design, Static Timing Analysis and Physical Verification
I am ASIC digital designer engineer, always keen to explore new alternatives, methodologies, designs. I like challenges and always proactive to help.
Microwave/RF Electrical Engineer. Love learning new things.
I am a PhD researcher in Electronic Engeneering at the University of Salerno, Fisciano, Italy. My main interest is the digital design of low power HW architectures for efficient signal processing acceleration.
In the electronic age, privacy is our shield — allowing us to reveal ourselves by choice. As the musica universalis guides the universe in harmony, so should our creations. Let's ignite a new Renaissance, driven by humanism and curiosity, a harmonised future of automated world, echoed with the music of human potential. 一期一会
CSE Professor at the University of Notre Dame
Seasoned VLSI professional with experience in complete chip design flow, domain experience data communication and telecom.
I am electronics engineer with 30years experience. I have very good expertise in IC packaging.
Computer Engineer at the University of Notre Dame
ASIC Designer with experience in Back-end & Front-end stages for ASIC design flow.
MSECE student at Ohio State University with focus on Analog & Mixed Signal VLSI circuits
I am a researcher in VLSI domain and Assistant Professor at DIAT India
Fresh Electronics and Computer Engineering graduate from Nile University with magna cum laude distinction. Interested in computer architecture design using AI. Have an experience with digital IC design, data analysis, machine learning, software engineering, and system administration. Currently, working at the NISC research center in Nile University as a part-time research assistant in the field of microarchitecture design.
From Mining Gems in the field to mining data about gems and developing bleeding edge Gemological/Geological/Geophysical/Geochemical/Geospatial/Spectroscopic and other Survey, Testing, Measuring, Databasing, Retrieval, and Analytical Devices/Software/Tradecraft as well as beyond crystal unit level precision automated faceting/cutting/polishing/cabbing/carving/lapidary instruments and even 500 picometer diameter diamond polish... I do it all. Anyone in the industry wanting to spice up and drastically increase the efficiency and ROI on their wafer lapping/polishing capabilities: help me...help you...get ahead of the EUV/DUV/3nm and finer processes (my system has an RI value of less than 500pm... THAT is smaller than 8 carbon atoms in a cubic formation...carbon...not silicon...
I have recently completed a course in VLSI Design and Verification. During my training period, I have done two projects: Router Design and Verification and the second one is UART Protocol.
I am software engineer of 20+ years experience in board bring up of multiple SoCs in Linux / QNX/RTOS/Baremetal. Mostly done projects on automotive and industrial automation domains
My research interests include systematic circuit synthesis techniques, modeling and simulation of linear and nonlinear circuits and systems, design and applications of fractional order chaotic oscillators, multi-objective optimization, evolutionary algorithms, and analog and mixed-signal design automation tools.
Embedded Software designer
Hao-Yen Tang received his PhD degree from UC Berkeley Advised by Prof. Bernhard E. Boser, his PhD research, PMUT ultrasonic fingerprint sensor, convince InvenSense senior management to make a heavy investment to take this technology to mass market. At InvenSense he’s leading a multi-disciplinary system team for the next generation ultrasonic fingerprint sensor bringup, characterization and calibration, coordinating the works from different field including acoustic, MEMS, CMOS, FW, and SW. Currently, he serves as CTO/Co-Founder in the startup company UltraSense Systems. The company is aiming to transform any surface material into a Touch/Press user interface with it’s proprietary PiezoMEMS-CMOS technology. Dr. Tang is the recipient of 2016 ISSCC Best Paper Award (Lewis Winner Award for Outstanding Paper), 2015 SSCS Pre-Doctoral Award and 2015 ADI Outstanding Student Designer Award. Currently he holds 20+ granted patents, 20+ publications, and 2000+ citations.
Senior security researcher, compiler/binary hacker, NFC ninja, hardware hacker with a FPGA hammer. Previously Pay Security.
I am an alumnus of Masters in Electrical Engineering from Department of Electrical Engineering, University of Engineering and Technology, Lahore; the project should be shipped there. The address is: University of Engineering and Technology, Main Campus, G. T. Road, Lahore, Pakistan. Postal code: 39161
Software developer / electronics enthusiast
I'm a BTech Electronics and Instrumentation graduate and an electronics enthusiast who was inspired by the open-source silicon technology and it's accomplishment and aim to build a career for myself in VLSI specifically as an ASIC Physical Design Engineer.
I am a passionate seeker of beneficial knowledge. I am into hardware design technology.
Technical Program Manager at Efabless Corporation
Director - RTL Mfra Tech
Berna Örs received the Electronics & Communication Engineering degree and the MSc degree in 1995 and 1998, respectively, both from the Istanbul Technical University (ITU), Turkey. She received the Electrical Engineering degree in applied sciences from the Katholieke Universiteit Leuven, Belgium, in 2005. Currently, she is a Professor at ITU. Her main research interests include cryptography, embedded systems, and side-channel attacks.
Electronic engineer specialized in FPGA devices.
I'm an person who is interested in electronics and computers my whole life. I like to design chips and pcb's.
Digital ASIC designer @ SenCure
I am a professor in computer engineering at the Faculty of Computer and Information Science, University of Ljubljana, Slovenia. My research interests include computer architecture and organization, parallel processing, computer arithmetic, embedded systems, and VLSI design.
Learning to build brain-inspired Neuromorphic chips. I used to wrestle with GPUs for graphics and AI. Previously at Unity Technologies and Electronic Arts.
Electronics Enthusiast with a passion for ML innovation
I am a recent graduate with a Major in Electronics and Telecommunication Engineering and a minor in computer engineering.
PhD in Electrical Engineering
Hellow My self Ali Gul currently pursuing my bacholar degree in Telecommunication Engineering From Quaid-E-Awam University Of Engineering Science & Technology Nawabshah and Hunger of gain some practicle knowlwdge in Circuit Design And Networking
I am a highly skilled and motivated Integrated Circuit (IC) Designer with expertise in both schematic and layout design and verification. Throughout my career, I have played a key role in the development of multiple image sensor Readout Integrated Circuits (ROICs), from initial concept to final production. My key strengths include: • Schematic Design and Verification: I have extensive experience in designing and verifying top-level schematics and novel digital IP blocks for ROICs. I am proficient in using Verilog-A, PWL models, and SPICE netlists for comprehensive validation. • Layout Design and Verification: I possess a strong understanding of physical design principles and a proven track record of owning physical design for complex ROICs, including floor planning, top-level integration, and signoff. I have expertise in 3D IC integration and have developed reusable block-level layouts for various digital and analog IPs. • Design Enablement: I am passionate about creating efficient design flows. I have pioneered an open-source digital design flow and a TSV routing flow, established methodologies for 3D IC validation, and customized Calibre rules for advanced designs. I am a results-oriented individual with a keen eye for detail and a passion for innovation. I am proficient in various EDA tools and PDKs and possess excellent problem-solving and analytical skills. I am eager to contribute my expertise to a team that is developing cutting-edge imaging technologies
RTL Design, GDS, VLSI
Design Verification Engineer with a keen sense of interest in Computer Architecture and RTL Design
I am a final year Computer engineering student at Habib University. I am currently focused on in-depth study of RISCV architecture, and SoC design for Robots.
Open Hardware Scientist
Cornell Tech ECE Master of Engineering Grad '24. Interested in startups and easier access to chip design and manufacturing!
Since 2001 I have worked for a small IC Layout design firm located in Wilsonville, Oregon called Coast-to-Coast Layout Design Inc. We provide full-custom mask design services to big semiconductor partners, both digital and analog/mixed-signal. I began my career as a part-time Linux systems administrator, and was taught mask design by my mentor and boss, then over the past couple decades I moved up the ranks to my current GM position where I am responsible for most day-to-day operations and management of multiple mask design teams who are very highly valued by our customers that rely on our services to meet tough tapeout schedule and quality requirements. I'm here because I'm planning to use open-source EDA tools to help train new mask designers to help grow my company.
Greetings! I, Devang Sharma am a B.Tech final year student studying at Jaypee Institute, Noida. I am a VLSI-enthusiast and posses moderate to advanced-level skillset(at B.Tech level). I have studied about ASIC Design Flow and learnt several HDLs(Verilog, SV, UVM).
Experienced ASIC Digital Design and Physical Implementation Enthusiast
Pre-Final year at EEE, NITK. Looking to get hands dirty with an immense curiosity and interest in fields (and not limited to) Digital Design, CPU architecture and other fields under computer engineering. Crazy about new market innovations and always looking forward to new connections.
