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"profiles" search for "skills": genus

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Number of Results: 9

wajeh ul hasan

I have been delving into the IC design industry for the last 3 years. I started with circuit designing on Virtuoso and am now working with the APR flow for the last 1 year

Skills

cadence genus cadence innovus Cadence Virtuoso

Area of Expertise

Digital: Placement and Routing

Rodrigo Nogueira Wuerdig

Skills

C/C++ Cadence Virtuoso Calibre Innovus Genus

Area of Expertise

Academic: Student CAD: Scripting CAD: Tool Development Digital: Placement and Routing Digital: RTL Digital: Synthesis Miscellaneous: Cryptography System: FPGA Programming

Sajjad Ahmed

I am an graduate student of computer system engineering at Usman Institute of Technology. and working on RISCV based SoC designs since 2019 in Microelectronics Research Lab.

Skills

C C++ genus synthesis innovus digital implementation Matlab System Verilog

Area of Expertise

Academic: Research

Ali Sabir

Skills

Cadence Virtuoso Verilog Cadence innnovus Cadence Genus

Area of Expertise

Academic: Research Academic: Teaching Digital: Placement and Routing Digital: RTL Digital: Synthesis

Gowtham

Skills

C/C++ Cadence Virtuoso Matlab Python Verilog genus

Area of Expertise

Academic: Student Digital: RTL

I have done electronic engineering from University of Engineering and Technology Peshawar in 2021, currently, i am doing MS in Electrical Engineering (Specialization in IC Design) from National University of Computer and Emerging Science(FAST-NUCES).

Skills

Cadence Genus Cadence Innovus Cadence Virtuoso Verilog

Area of Expertise

Analog: Layout Digital Synthesis Digital: Placement and Routing Digital: RTL

karunakar reddy kesamreddy

I am a professional in the field of Chip Design, Primary working on Synthesis, Physical Design, Static Timing Analysis and Physical Verification

Skills

Cadence Virtuoso Cadence Innovus Cadence Genus Synopsys Prime Time Synopsys IC Compiler 2 Synopsys Fusion Compiler Synopsys Design Compiler Tweaker Synopsys IC Validator Seimens Calibre

Area of Expertise

Analog: Design Digital: Synthesis Physical Design Physical Verification Static Timing Analysis

M Naveed

MS IC Design Student

Skills

Cadence Genus Cadence Innvous Openlane Verilog

Area of Expertise

Academic: Student

Dhanunjaya Achari Kammari

A dedicated Physical Design Engineer aspiring to craft silicon for real-world applications.

Skills

Cadence Genus Cadence Innovus Cadence Virtuoso Calibre Python Tcl/Tk Verilog

Area of Expertise

Physical Design Scripting Synthesis