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"profiles" search for "skills": compiler
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Number of Results: 10

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Andre5

I am Electronic Engineer from Chile, I like DSP and radioastronomy applications an ordinary guy

Skills

C/C++ System Verilog Verilog Design Compiler Descartes Formality ICC ICC2 DFT Xilinx ISE design suite FPGA full flow programming

Area of Expertise

Circuits: Filters Circuits: Signal Processing Digital: Placement and Routing System: FPGA Programming System: Quality Assurance System: Test Programming
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Ashraf Mohamed

Highly-motivated Engineer looking to gaining new challenge in Analog IC design and RF/ mm-wave IC Design. Organized, hardworking, and energetic. Wishing to leverage my passion for technology and design.

Skills

Cadence Virtuoso Calibre Python HSPICE Custom Compiler Shell Scripting

Area of Expertise

Analog: Design Analog: Layout
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Gabriel Sanca

Skills

Hercules ngspice Python SPICE Opus pcells Custom Compiler

Area of Expertise

Academic: Research
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Zhiyang Ong

Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.

Skills

C/C++ Cadence Encounter Cadence NC-Verilog Cadence Virtuoso Electric CAD Electric VLSI Design System Matlab Mentor/Siemens EDA ModelSim ngspice Octave Perl Python Software Developer Synopsys Avanwaves Synopsys Cosmos Synopsys Design Compiler Synopsys HSPICE Synopsys NanoSim Synopsys PrimeTime System Verilog System-C Tcl/Tk Verilog VHDL Xilinx ISE

Area of Expertise

Academic: Research Academic: Student Analog: Design Analog: Modeling Analog: Simulation Analog: Verification CAD: Scripting CAD: Tool Development Circuits: Communication Circuits: Filters Circuits: Memory Circuits: Microcontrollers Circuits: Signal Processing design space exploration of VLSI system designs Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Neural Networks RTL code generation SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: Test Programming VLSI layout design
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Yunus Dawji

I am a PhD candidate with analog and digital design experience.

Skills

Cadence Encounter Cadence Virtuoso Calibre SKILL ic compiler

Area of Expertise

Analog: Design Digital: Placement and Routing Digital: RTL Digital: Synthesis
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Jeehoon Kang

Associate Professor at KAIST

Skills

programming languages compiler RTL design

Area of Expertise

Academic: Research Academic: Teaching Digital: RTL
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Teng-Kiat Lee

Skills

Cadence Virtuoso Custom Compiler Synopsys

Area of Expertise

EDA Custom Design
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karunakar reddy kesamreddy

I am a professional in the field of Chip Design, Primary working on Synthesis, Physical Design, Static Timing Analysis and Physical Verification

Skills

Cadence Virtuoso Cadence Innovus Cadence Genus Synopsys Prime Time Synopsys IC Compiler 2 Synopsys Fusion Compiler Synopsys Design Compiler Tweaker Synopsys IC Validator Seimens Calibre

Area of Expertise

Analog: Design Digital: Synthesis Physical Design Physical Verification Static Timing Analysis
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Joao Fernandes

Skills

Cadence Virtuoso Matlab Verilog-A Synopsys Custom Compiler Spice

Area of Expertise

Analog: Design Analog: Verification A&Ms Desing
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Mohammed Salah

Experienced ASIC Digital Design and Physical Implementation Enthusiast

Skills

Cadence Encounter Tcl/Tk Verilog Synopsys Design compiler (DC) Synopsys Formality Synopsys ICC Synopsys ICC II Synopsys PrimeTime QuestaSim Vivado

Area of Expertise

Digital: DFT Digital: Placement and Routing Digital: RTL Digital: Synthesis