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"profiles" search for "skills": RTL design
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Number of Results: 6

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Rohit Khanna

Hardware Design Engineer with 7 years of experience in RTL/SoC/FPGA Design, Integration, and Verification. Proficient in Front End Design tools and methodologies. Passionate about IC Design/Fabrication, AI, and IoT prototyping.

Skills

RTL Design SoC Integration System Verilog Verilog

Area of Expertise

CAD: Scripting Digital: RTL System: FPGA Programming
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Pradeep Kumar Velidi

I am a young student, growing high with a passion for VLSI. I am highly interested in working on high-speed low-power RTL chip design.

Skills

Cadence Virtuoso Matlab Python System Verilog Verilog vivado c RTL Design

Area of Expertise

Academic: Student
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Jeehoon Kang

Associate Professor at KAIST

Skills

programming languages compiler RTL design

Area of Expertise

Academic: Research Academic: Teaching Digital: RTL
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Harsh Rajeshbhai Vagadiya

VLSI Enthusiastic

Skills

Verilog RTL Design

Area of Expertise

Academic: Student
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Raj Nirmal

Skills

System Verilog Verilog computer Architecture RTL Design

Area of Expertise

Academic: Student
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Ashwin Krishna Mani

I am currently a Design Verification Intern and I am looking to bolster my thought processes more in this world of RTL Design and Computer Architecture

Skills

C/C++ Python System Verilog Verilog RTL Design Computer Architecture

Area of Expertise

Academic: Student