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Engineer at Science Corporation in Alameda, CA

C/C++ Cadence Virtuoso Python System Verilog Mixed Signal Design

Analog: Design Analog: Layout CAD: Scripting Digital: RTL

System Verilog ASIC FPGA UVM UPF Mixed signal design AMS Real number modeling

Mixed signal design and verification

Experienced circuit and chip designer and design manager with major interest in low voltage low power analog design.

Cadence tools, analog and mixed signal design

Academic: Teaching