I'm an AMS Design engineer. I like the IC design world and my recent goal is to be a scientist :)
I have been working on Analog/Mixed-Signal Integrated Circuits design since last 16 years. I graduated from NED UET, Karachi in 2001 and then worked with Avaz Networks, a Silicon-Valley Company on RTL design and verification of a high-density Line Echo Cancellation Engine for a couple of years. Joined Linkoping University, Sweden in 2003 for Masters in SOC, which concluded with a Masters Thesis on Sigma-Delta Modulators with Fraunhofer Institute of Integrated Circuits, Germany in 2005. The same year I joined University of Trento and Fondazione Bruno Kessler, Trento, Italy for my PhD on Readout Interface Design for MEMS Capacitive Microphones. Worked with ST-Microelectronics, Milano and Analog-Devices, Copenhagen as a Guest PhD Student. This Phd results in 20+ publications and 2 patents with 3 successful MEMS Readout ASICs.
I have more than five years’ experience in electronics integrated circuits industry. I have been involved in more than six silicon runs which were all successful and meeting expectations.
I am a experienced analog and mixed-signal circuits designer, using standard and/or custom circuits ( external IPs or from my own design ).
Developer of open source EDA tools on Open Circuit Design
Analog IC design engineer with expertise in designing analog building blocks variable gain amplifiers, active filters, frequency synthesizer (integer-N PLLs), voltage regulators.
VLSI circuit design engineer with significant experience in microprocessor design in semiconductor processes from 65nm to 10nm. Provided register file designs and design training for Intel Big Core and SOC projects. Helped create semi-automated array layout methodology. Established cross-organizational methodology for variation analysis in register files. Converged memory IP handling across multiple organizations.
Valparaiso University - College of Engineering - ECE professor
AMS Design Engineer Love Electronics and programing
I am a full custom analog and mixed-signal IC design consultant. I have been consulting for over 22 years following 12 years as a staff member at MIT Lincoln Laboratory.
We are building a community of OSHW Product Creators. Our focused mission is to simplify the process of smart product creation and making it available to everyone. We believe in Open Source Hardware as the foundation for addressing the massive and divergent forms and features of the new connected world.
I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.
Manager of Universal Avionics System Corporation(UASC) PLD design group. This group is tasked with designing, implementing and approving, in accordance with RTCA/DO-254 guidance, all ASIC/FPGA used in the Universal Avionics product line.
Electrical Engineer M.Sc. Microelectronics
Computer Science Engineer with extensive hardware knowledge.
Embedded System Engineer
I am an Analog/mixed signal IC designer. I worked with different technologies like ams035, xh035 and st 130nm.
I am an EMC Specialist working at Renault and currently looking to fill my free time with interesting projects (Hardware, EMC, Design, Simulation)
Recent college graduate from San Jose State University with Masters in Electrical Engineering degree. Specialization - Digital Design and Verification.
Analog/Mixed-Signal IC Design Engineer
BSEE graduating senior with a focus in digital design. I have taken coursework in Analog, Digital, Mixed Signal and RF IC design, and have experience using Cadence's tool suite as well as NI's AWR. I have also done multiple EDA centric courses in validation, formal and functional verification and Digital IC Testing
MSC in Electrical Engineering BSC in Electronics Two patents in mathematical software in Engineering design and digital signal processing utility box Undergo private research for commercial use in the areas of very high frequency analog and digital circuits
I am a microelectronic engineer/CMOS designer with an emphasis on digital & low-power electronics and front-end circuitry. I am an academic at The University of Sydney, Australia and working on devices to data solutions for a range of problems such as unmet needs in electronic monitoring/sensing and interventions in neurological disorders.
I am an graduate student of computer system engineering at Usman Institute of Technology. and working on RISCV based SoC designs since 2019 in Microelectronics Research Lab.
Love for ELectronics Chips Designing, Eager for knowledge. Close to Nature and meet me on the success road.
Researcher, thinker, innovator, amateur, and little science... God almighty believed
I am recently completed my post-graduation in VLSI and Embedded system from coep pune(India). I like to work in a backend design of VLSI.
mmwave RFIC / mmwave RF designer
Electrical Engineer interested in the design of mixed signal ASICs
Full time: Electronics Engineer with an interest in embedded systems solutions. I can take a project goal and design, develop, prototype, program, validate an embedded system reaching that goal. Part-time: Maker, interested in rapid prototyping, my lab has basic machines: CO2 Laser cutter, 3d printers, small milling machine. I've built 3 of my own 3d printers.
As an experienced Electronic Engineer with a solid foundation in FPGA design, embedded systems, and IoT, I specialize in high-level hardware programming and real-time signal processing. With expertise in RTL, RISC-V, Verilog, SystemVerilog, and VHDL, I bring a robust understanding of digital design to my work. My professional background includes over a decade in the PCBA assembly industry, where I programmed and configured SPI and Chip Mounter machines, managed production processes, and handled CAD and Gerber files for precision assembly. Additionally, I am well-versed in designing and testing complex circuits using tools like Proteus, Fritzing, and Altium, with a particular interest in the emerging role of AI in electronics. As a career coordinator, former educator in electronics, and an active researcher, I blend practical industry experience with a passion for fostering innovation and teaching in the electronics field. My recent projects involve integrating IoT with embedded solutions, exploring the intersection of FPGA technology with real-time applications, and continually expanding my knowledge in artificial intelligence.
Taher Kourany joined Scenario Design Services, Cairo, Egypt as a Senior IC Design Consultant in 2016. He received B.Sc Degree in electronics and communications engineering from Ain-Shams University, Cairo, Egypt, in 2012. He received M.S. degree in electronics from the American University, Cairo, Egypt, in 2015. Until October 2015 he was a Research Assistant with the Center of Nanoelectonics and Devices Research Labs at Zewail City for Science and Technology. Mr. Kourany has published papers in the field of time complexity reduction algorithms of floorplan representations, area and wirelength minimization, Pareto-front multi-objective optimization algorithms of highly chaotic systems. His current research interests include high linearity Power Amplifiers, time complexity reduction algorithms, data structures, parameters estimation of highly chaotic systems, and the synthesis of analog IC design and layout.
Sr. Electrical Engineer with 40 years of experience, doing R&D, circuit design from concept through layout and to production in Aerospace, Automotive, Industrial and Gas and Oil down-hole business sectors.
I am currently in my junior year studying computer engineering at the University of Notre Dame. Alongside that, I am pursuing a concentration in cybersecurity and a minor in engineering corporate practice. My curiosity was initially drawn to the puzzle-like nature of security problems, which led me to major in Computer Engineering in an effort to dissect both the hardware and software sides of computer systems and expose their vulnerabilities. The more I learned about cybersecurity, the more I realized its criticality in safeguarding individuals and organizations and its ever-growing prominence in our tech-driven world, especially within software development. Throughout my undergraduate career, I have taken on various leadership positions, from acting as the Vice President of my university's Engineers Without Borders chapter to leading development teams at CS For Good. I expect to graduate in May 2025, and I am currently interested in an internship position for the summer of 2024.
I am currently in my junior year studying computer engineering at the University of Notre Dame. Alongside that, I am pursuing a concentration in cybersecurity and a minor in engineering corporate practice. My curiosity was initially drawn to the puzzle-like nature of security problems, which led me to major in Computer Engineering in an effort to dissect both the hardware and software sides of computer systems and expose their vulnerabilities. The more I learned about cybersecurity, the more I realized its criticality in safeguarding individuals and organizations and its ever-growing prominence in our tech-driven world, especially within software development. Software engineering complements that passion but adds a layer of creativity and ingenuity that fuels my drive to develop programs and systems that help serve people all over the world. I strive to build solutions that are not only resource-efficient but also sustainable, scalable, and adaptable. Achieving this goal requires a relentless passion for learning about available and emerging technologies – a skill I am proud to have. I am fascinated by the ever-evolving landscape of tech innovation, and it is this fascination that motivates me to delve deeper into the world of technology, continuously seeking out new knowledge and skills to ensure I stay at the forefront of this dynamic industry. Throughout my undergraduate career, I have taken on various leadership positions, from acting as the Vice President of my university's Engineers Without Borders chapter to leading development teams at CS For Good. I expect to graduate in May 2025, and I am currently interested in an internship position for the summer of 2024.
I have recently completed a course in VLSI Design and Verification. During my training period, I have done two projects: Router Design and Verification and the second one is UART Protocol.
Director - RTL Mfra Tech
As a VLSI enthusiast, I completed a 6-month internship as a NAND product engineer at Micron Technology where my work comprises of post-silicon validation, data analysis using JMP, and testing NAND components under varying PVT conditions in DDR3 and LPDDR4. I'm passionate about CMOS and have experience simulating NAND output drivers through HSPICE simulations in collaboration with the design team. Additionally, I have proficiency in System Verilog, RTL design, and a solid grasp of digital IC, analog IC, and physical design. I hold a master's degree in Microelectronics from BITS Hyderabad and a bachelor's degree in ECE from Gayatri Vidya Parishad. I achieved a GATE ECE score of 571 with an All India Rank (AIR) of 1404 in 2023. devadeepreddi20@gmail.com
