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C/C++ Cadence Virtuoso Perl Python Verilog VHDL

Academic: Research Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification

Working on ASIC, FPGA design flows. Interested in VLSI Design.

C/C++ Matlab Python Verilog

Academic: Research Academic: Student System: FPGA Programming

An enthusiast of the Open Source World.

C/C++ Matlab Python Verilog Linux

Academic: Student