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Designer specialized on VLSI radiation tolerant architectures and circuits

System Verilog T-Spice Tanner L-Edit UVM-Functional Verification

Academic: Research Circuits: Communication Digital: RTL Digital: Verification

I am ASIC digital designer engineer, always keen to explore new alternatives, methodologies, designs. I like challenges and always proactive to help.

C/C++ Cadence Encounter Matlab Python System Verilog Verilog

Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis