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Number of Results: 4

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Bhawandeep Singh

Linkedin - https://www.linkedin.com/in/bhawandeep-singh-1b164517/ PhD student in CSE department in UCSC, advised by Prof. Jose Renau. My areas of majors are CPU design, digital design and embedded software.

Skills

C/C++ Python System Verilog Tcl/Tk Verilog

Area of Expertise

Academic: Research Academic: Student Academic: Teaching Circuits: Microcontrollers Digital: RTL System: FPGA Programming
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Bob Ledzius

35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.

Skills

C/C++ Leadership Matlab System Verilog Tcl/Tk Verilog

Area of Expertise

Business: Design Services Business: Management Business: Patents CAD: Scripting CAD: Tool Development Circuits: Filters Circuits: Microcontrollers Circuits: Signal Processing Digital: RTL Digital: Verification Miscellaneous: Cryptography SoC: Verification System: FPGA Programming System: PCB
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Baher Nicola

Skills

C/C++ Matlab Software Developer System Verilog Verilog VHDL

Area of Expertise

Circuits: Microcontrollers Circuits: Signal Processing System: FPGA Programming
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Dimitar

Skills

Spectre Verilog

Area of Expertise

Digital: RTL Digital: Verification