Efabless Logo

Tag Search

"profiles" search for "interests": SoC Verification
Open Search

Number of Results: 2

entry image

Mohit R

Graduate equipped with a Bachelor of Engineering in Electronics and communication with a concentration in Semiconductor and VLSI design with hands-on experience in CAD tools and to join a reputable organization to begin a fulfilling, lifelong career.

Skills

C/C++ Cadence Virtuoso Electric CAD Python SKILL Verilog

Area of Expertise

Analog: Layout
entry image

Paulo Roberto Bueno de Carvalho

Skills

C/C++ Cadence Encounter System Verilog Verilog

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification