Efabless Logo

Tag Search

"profiles" search for "skills": systemverilog
Open Search

Number of Results: 3

entry image

Lachlan Cuskelly

Aspiring analog IC designer

Skills

C/C++ Matlab Python LTSpice/Multisim Verilog/SystemVerilog Unix Shell FPGA for Prototype development Electronics Lab Experience Altium Designer

Area of Expertise

Academic: Student
entry image

Renaud GILLON

Electrical engineer with PhD in micro-electronics, and more than 23 years experience in the automotive industry. Specialized in the development of CAD tools to support mixed-signal and smart-power IC design. Founder of SYDELITY b.v. a start-up company offering services and products accellerating system-level simulations.

Skills

C/C++ Cadence Virtuoso Mentor Questa-ADMS Python Tessent Defectsim Verilog-A(MS) VHDL-AMS VHDL-D SystemVerilog Modelica

Area of Expertise

Analog Behavioral modeling EMC ESD Fault injection Power System identification
entry image

liu jiangqing

de worker

Skills

Python systemverilog

Area of Expertise

Analog: Verification