Analog full custom design experience of Low power VOltage regulators, Bandgap reference, calibration circuits and common mode receiver. worked on SERDES IP (up to 12Gbps) compliant with USB 3.1 and SATA protocols. AS ESD ENgineer for SERDES IP Improved existing ESD network simulation strategy and ESD network for robust ESD performance reliability and automated existing current density flow for ESD for better efficiency. Technology Nodes: 14nm(FINFet), 28nm(FDSOI) 28 nm,40nm,90nm,180nm (Bulk)
An energetic semiconductor professional with varied experience in the field of research, teaching and IC design. 📌 More than 6 years of experience in analog and mixed signal IC design. 📌 3 years of mentoring experience in analog circuit and layout design. 📌 Been part of the 4 complete IC development project. 📌 Inventor and co-inventor of 2 patents (filed) in the field of high-speed data path communication. 📌 Published few research papers with more than 30 engineering citations. 📌 6 month experience as a lead role in standard cell library development in a leading semiconductor organisation. 📌 more than 4 years of teaching experience in under-graduate electronics engineering courses.
Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.