Tag Search Results

Tag Search

"profiles" search for "interests": RTL Design

Open Search

Number of Results: 20

Buğra Tufan

Skills

C/C++ Matlab Python Tcl/Tk Verilog VHDL

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification

Ahsan Ali

Passionate Electrical Engineer with interest in computer architecture and SoCs.

Skills

C/C++ Matlab Python System Verilog Verilog

Area of Expertise

Academic: Student Circuits: Microcontrollers Digital: RTL Digital: Synthesis Digital: Verification

Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,

Skills

Cadence Encounter Cadence Virtuoso Calibre ngspice Python Tcl/Tk Verilog

Area of Expertise

Analog: Design Digital: Placement and Routing Digital: RTL Digital: Synthesis System: FPGA Programming

Dilip Singh

A researcher and VLSI guy

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Matlab Python System Verilog Tanner L-Edit Tcl/Tk Verilog

Area of Expertise

Academic: Research Circuits: Filters Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis System: FPGA Programming

Shruti Prakash Gupta

I am a Senior Undergraduate in Electrical Engineering Department at IIT Gandhinagar, India. VLSI Design and the ability to tweak at the hardware level interest me a lot!

Skills

C/C++ Cadence Virtuoso Matlab Python System Verilog Verilog

Area of Expertise

Academic: Student CAD: Scripting Circuits: Microcontrollers Digital: RTL Digital: Verification SoC: Verification System: FPGA Programming

Pradeep Purushothaman Vadakkodathu

Skills

C/C++ Matlab System Verilog Tanner L-Edit Tcl/Tk Verilog

Area of Expertise

Digital: RTL Digital: Verification SoC: Verification System: FPGA Programming

Md Adil Raza

Skills

C/C++ Matlab Python Scilab Verilog

Area of Expertise

Academic: Student

RECEP GÜNAY

Received B.S. degree from Electrical and Electronics Engineering in Middle East Technical University, Turkey, in 2019. Currently, pursuing M.S. degree from Electronics Engineering in Bogazici University, Turkey. Research interests are computer architecture, hardware security and secure memory architecture

Skills

C/C++ Cadence Virtuoso Magic CAD System Verilog Verilog

Area of Expertise

Academic: Student Circuits: Memory Circuits: Microcontrollers Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography System: FPGA Programming

Aditya Mudgal

Doing Mtech in VLSI Design from IIIT Bangalore

Skills

C/C++ Cadence Virtuoso System Verilog Verilog

Area of Expertise

Academic: Student

Geethanand N

Ex intel professional with over 5 years of experience in front end Vlsi

Skills

Perl System Verilog Tcl/Tk Verilog

Area of Expertise

CAD: Scripting Digital: RTL Digital: Verification SoC: Verification

Shubham Tonde

I am recently completed my post-graduation in VLSI and Embedded system from coep pune(India). I like to work in a backend design of VLSI.

Skills

Digital design pel sta Verilog

Area of Expertise

Digital: Placement and Routing Digital: RTL

Pruthvi raj Venkatesha

Skills

C/C++ Cadence Virtuoso System Verilog Verilog

Area of Expertise

Academic: Student

Pradeep C

I hold a Doctoral Degree in ‘Information and Communication Engineering,’ with 22+ years of experience in engineering education in various capacities. I have more than 30 research articles, presented and published in various National, International Journals and Conferences. My research interests are in the following domains and are not confined to VLSI, AIoT, Intelligent Transportation for Smart Cities in India, FPGA-based System Design, etc. My professional membership includes a Fellow, in the Institution of Engineers (India), a Fellow in the Institute of Electronics and Telecommunication Engineers, a Senior Member of IEEE, and a member of ISTE & ACM.

Skills

Leadership Verilog

Area of Expertise

Academic: Research Academic: Teaching Digital: RTL

Pradeep Kumar Velidi

I am a young student, growing high with a passion for VLSI. I am highly interested in working on high-speed low-power RTL chip design.

Skills

Cadence Virtuoso Matlab Python System Verilog Verilog vivado c RTL Design

Area of Expertise

Academic: Student

Dhruva Hegde

Masters Student (Integrated Circuits and Systems) at IIT Bombay.

Skills

Python Verilog VHDL

Area of Expertise

Academic: Research Circuits: Signal Processing Digital: RTL Digital: Synthesis

devang gajjar

Skills

C/C++ Perl Python System Verilog Verilog VHDL

Area of Expertise

Circuits: Microcontrollers Digital: RTL Digital: Synthesis Digital: Verification System: FPGA Programming

Harsh Rajeshbhai Vagadiya

VLSI Enthusiastic

Skills

Verilog RTL Design

Area of Expertise

Academic: Student

Raj Nirmal

Skills

System Verilog Verilog computer Architecture RTL Design

Area of Expertise

Academic: Student

karunakar reddy kesamreddy

I am a professional in the field of Chip Design, Primary working on Synthesis, Physical Design, Static Timing Analysis and Physical Verification

Skills

Cadence Virtuoso Cadence Innovus Cadence Genus Synopsys Prime Time Synopsys IC Compiler 2 Synopsys Fusion Compiler Synopsys Design Compiler Tweaker Synopsys IC Validator Seimens Calibre

Area of Expertise

Analog: Design Digital: Synthesis Physical Design Physical Verification Static Timing Analysis

SAMRAT CHHABRA

Enthusiastic electronics engineer passionate about the digital VLSI domain.

Skills

C/C++ Matlab System Verilog Verilog VHDL

Area of Expertise

Digital: DFT Digital: RTL Digital: Synthesis Digital: Verification