PhD student working on a superconducting FPGA design aiming to work on neuromorphic computing in the future.
ASIC and FPGA design and verification Engineer with a sideline in bring devops to Hardware projects
Creation, Paasion, Action are my three main characteristics. I am a Project Manager with Communication Engineering backgound in ICT field. Focus on the topic of IC design, OS design, Cloud computing and Quantum computing.
VLSI DOMAIN SKILLS --------------------------- • Digital Electronics • HDL: Verilog • HVL: System Verilog • TB Methodology: UVM • Protocols: APB, UART, I2C, SPI • EDA Tools: Modelsim, Quartus Prime, Questasim. VLSI RTL SKILLS ---------------------- • Digital Skills : Combinational and Sequential circuits • FSM • Memories • Verilog : Data types • Operators • BA and NBA • Delays in Verilog • Begin-end and fork-join Blocks • System tasks and Function • Compiler directive • FSM Coding. VLSI VERIFICATION SKILLS ------------------------------------ • System Verilog HVL: Data Types • Memories • Interface • OOPS • Constraint Randomization • Threads • Functional coverage • CRCDV • SV Testbench (Hands on SV Testbench) • Universal Verification Methodology: UVM Objects and Components • UVM Factory • UVM Phases • UVM Configuration • TLM • Virtual Sequence and Sequencer • UVM Testbench (Hands on UVM Testbench).
I am an Engineer and Project Manager in Software and Hardware Space !
I am really interested in Research for progressing my work in RF electronics
