I am a PhD. Telecommunication Engineer with 25 years of working experience in the industry. I started my career in 1997 as an IC Design Engineer, then I moved to other technical and management roles in the semiconductor and aerospace industries. Since 2017 I am also teaching IC Design at University for MsC. graduate students.
Engineer / VP
A software developer, technology manager, and hardware tinkerer aspiring to imbue slices of crystals with intelligence.
I have over thirty years of experience in the semiconductor industry, having worked in fab, EDA and design engineering. have built and led large, geographically distributed teams at a senior manager level. I am passionate about developing talent and skills, particularly in young people from socio-economically underprivileged backgrounds.
RTL design engineer with experience developing mobile GPUs (Samsung), high-end networking ASICs (Juniper) and CPU cores (MIPS). Co-author of lab manuals and online courses on FPGA design, RTL2GDSII flow and computer architecture. Founder of Verilog Meetup, a Silicon Valley and online community that develops open-source SystemVerilog examples targeting three niches: beginners, students who want to prepare for microarchitectural job interviews and university professors who want to avoid FPGA vendor lock (our examples are interoperable between Xilinx, Altera, Gowin and Lattice and compatible with ASIC flows, such as TinyTapeout and eFabless (in progress)).