Zhiyang Ong is a globetrotting, venturesome cultural chameleon tackling challenges related to U.N. Sustainable Development Goals, using a skill set that spans electrical engineering and computer science. He is a Ph.D. student at Texas A&M University's electrical & computer engineering department. He is currently working on noise-based logic and embedded deep learning, and had worked on problems in electronic design automation, VLSI formal verification, satisfiability modulo theories, network science (or complex systems), evolutionary computation, network optimization, and multi-objective optimization. He has also designed multiple VLSI circuits and systems, from SRAMs and processors to a Viterbi decoder and a tree adder. In his free time, he was recently working on solving the Quadratic Travelling Salesman Problem (QTSP) with his research collaborators, using an adiabatic quantum computer from D-Wave Systems.
RTL design engineer with experience developing mobile GPUs (Samsung), high-end networking ASICs (Juniper) and CPU cores (MIPS). Co-author of lab manuals and online courses on FPGA design, RTL2GDSII flow and computer architecture. Founder of Verilog Meetup, a Silicon Valley and online community that develops open-source SystemVerilog examples targeting three niches: beginners, students who want to prepare for microarchitectural job interviews and university professors who want to avoid FPGA vendor lock (our examples are interoperable between Xilinx, Altera, Gowin and Lattice and compatible with ASIC flows, such as TinyTapeout and eFabless (in progress)).
