Tag Search Results

Tag Search

"profiles" search for "interests": Computer Architecture

Open Search

Number of Results: 28

Ahsan Ali

Passionate Electrical Engineer with interest in computer architecture and SoCs.

Skills

C/C++ Matlab Python System Verilog Verilog

Area of Expertise

Academic: Student Circuits: Microcontrollers Digital: RTL Digital: Synthesis Digital: Verification

Aravind

I am a Application Engineer working for Cadence Design Systems and I facilitate the use of the Palladium Emulator at different Customers.

Skills

C/C++ Perl Python Verilog

Area of Expertise

ASIC Design/Verification Design Automation

Ganesh V

ECE undergraduate looking to gain expertise in Analog/digital design.

Skills

Cadence Virtuoso Python SKILL Software Developer Spectre Verilog

Area of Expertise

CAD: Scripting Digital: Verification

James Stine

Edward Joullian Endowed Chair in Engineering Oklahoma State University Department of Electrical and Computer Engineering VLSI Computer Architecture Research Group

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Magic CAD Matlab Netgen ngspice Octave Perl Python SKILL Spectre System Verilog Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research

Sunkeerth M

Passionate student of electronics and computer engineering

Skills

C/C++ Matlab Python VHDL

Area of Expertise

Academic: Student

Alperen Koyun

Beginner Digital Designer

Skills

C/C++ Matlab Python Verilog VHDL

Area of Expertise

Digital: RTL

Received B.S. degree from Electrical and Electronics Engineering in Middle East Technical University, Turkey, in 2019. Currently, pursuing M.S. degree from Electronics Engineering in Bogazici University, Turkey. Research interests are computer architecture, hardware security and secure memory architecture

Skills

C/C++ Cadence Virtuoso Magic CAD System Verilog Verilog

Area of Expertise

Academic: Student Circuits: Memory Circuits: Microcontrollers Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography System: FPGA Programming

Diego Dutra

Skills

C/C++ System Verilog Verilog VHDL

Area of Expertise

Academic: Research

Abdul Wadood

Final year student of Electrical Engineering at UET Lahore. Area of expertise is Digital Design, Computer Architecture and SOCs.

Skills

Python System Verilog Verilog

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification SoC: ESD

Maurya Patel

Skills

Verilog

Area of Expertise

Academic: Student

Nima Badizadegan

I am a digital and mixed-signal circuit designer.

Skills

C/C++ Magic CAD System Verilog Verilog

Area of Expertise

Analog: Design Business: Patents Circuits: Microcontrollers Digital: RTL System: FPGA Programming

Redwan

Skills

Cadence Virtuoso Calibre Python Spectre Tanner L-Edit Verilog

Area of Expertise

Analog: Layout Circuits: Memory

Govindu Sathvik Reddy

micro-architecture enthusiast | student at IIT Indore

Skills

C/C++ Matlab Verilog

Area of Expertise

Digital: RTL Digital: Synthesis

Cagri

Skills

C/C++ Perl Python Software Developer SPICE Opus VHDL

Area of Expertise

Business: Design Services Miscellaneous: Neural Networks SoC: Verification

varun mohan

Skills

C/C++ Python Verilog VHDL

Area of Expertise

Digital: RTL System: FPGA Programming

Mohit R

Graduate equipped with a Bachelor of Engineering in Electronics and communication with a concentration in Semiconductor and VLSI design with hands-on experience in CAD tools and to join a reputable organization to begin a fulfilling, lifelong career.

Skills

C/C++ Cadence Virtuoso Electric CAD Python SKILL Verilog

Area of Expertise

Analog: Layout

Rachid Karami

Skills

C/C++ VHDL

Area of Expertise

Academic: Research Academic: Student

Arya Reais-Parsi

PhD Student @ UC Berkeley, formerly SWE @ Google

Skills

C/C++ Python Software Developer Verilog VHDL

Area of Expertise

Academic: Research Academic: Student Academic: Teaching Analog: Layout CAD: Tool Development Digital: Placement and Routing Digital: Synthesis

Tseng BO-YU

Skills

C/C++ Matlab Octave Python System Verilog System-C Verilog

Area of Expertise

Academic: Student

Theodoric Xie

ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.

Skills

C/C++ Python Software Developer System Verilog Verilog

Area of Expertise

Academic: Research CAD: Scripting CAD: Tool Development Circuits: Signal Processing Digital: RTL Digital: Synthesis Digital: Verification SoC: Verification System: FPGA Programming

Gagan Gupta

I am an enthusiastic proponent of open source hardware. See my position paper on the topic: https://ieeexplore.ieee.org/document/7945172.

Skills

C/C++ Leadership System Verilog System-C Verilog VHDL

Area of Expertise

Academic: Research Business: Management Business: Marketing Business: Patents Business: Sales Digital: DFT Digital: RTL SoC: Verification

Muhammad Shoaib

Skills

Cadence Virtuoso Matlab Python Verilog Artificial Intelligence

Area of Expertise

Academic: Student

Zain Siddavatam

A Computer Architecture Enthusiast, Undergrad Student

Skills

C/C++ Python Verilog

Area of Expertise

Academic: Student Digital: RTL

牛诗然

A student wants to study ASIC design.

Skills

C/C++ Verilog

Area of Expertise

Academic: Student

Nigil Mohra

Skills

Cadence Virtuoso

Area of Expertise

Academic: Student

muhammad gamal rizq metwally

Fresh Electronics and Computer Engineering graduate from Nile University with magna cum laude distinction. Interested in computer architecture design using AI. Have an experience with digital IC design, data analysis, machine learning, software engineering, and system administration. Currently, working at the NISC research center in Nile University as a part-time research assistant in the field of microarchitecture design.

Skills

C/C++ Cadence Virtuoso Python System Verilog Verilog

Area of Expertise

Academic: Research Digital: RTL Digital: Synthesis

George Johnson

I am an engineering student in my 3rd year interested in a VLSI career i am still exploring the field and am currently interested in frontend design

Skills

C/C++ Cadence Virtuoso Leadership Python R

Area of Expertise

Academic: Student