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"profiles" search for "interests": CPU
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Number of Results: 15

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Bhawandeep Singh

Linkedin - https://www.linkedin.com/in/bhawandeep-singh-1b164517/ PhD student in CSE department in UCSC, advised by Prof. Jose Renau. My areas of majors are CPU design, digital design and embedded software.

Skills

C/C++ Python System Verilog Tcl/Tk Verilog

Area of Expertise

Academic: Research Academic: Student Academic: Teaching Circuits: Microcontrollers Digital: RTL System: FPGA Programming
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gb6612

Skills

C/C++ Cadence Virtuoso Leadership ngspice Perl System Verilog Verilog

Area of Expertise

Business: Management Digital: RTL Digital: Synthesis Digital: Verification SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: Quality Assurance
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Day Make

Master course student from JP

Skills

C/C++ Verilog VHDL

Area of Expertise

Academic: Student
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Dubravko Gacina

Embedded systems design engineer

Skills

C/C++ Python Software Developer

Area of Expertise

Circuits: Microcontrollers System: PCB
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Daniel Pacheco

I like to work with Lua and C as well Power ISA is my go to architecture.

Skills

C/C++ System-C

Area of Expertise

Analog: Design System: Fabrication Process
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Ufuk Yıldırım

Skills

C/C++ Verilog VHDL

Area of Expertise

Digital: DFT
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Mumuji

Skills

C/C++

Area of Expertise

Academic: Student
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Anthony Kung

Hi, I'm an Electrical & Computer Engineering + Computer Science student at Oregon State University.

Skills

C/C++ Python Software Developer System Verilog Verilog VHDL

Area of Expertise

Academic: Student Digital: RTL System: FPGA Programming
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Zachary Berkowitz

Skills

C/C++ Python Verilog KiCAD

Area of Expertise

Academic: Student
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Masahiro Suzuki

Skills

C/C++ System Verilog Tcl/Tk Verilog

Area of Expertise

Digital: Placement and Routing SoC: Floorplanning
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Syed Manzoor Qasim

Skills

Leadership Magic CAD Matlab System Verilog Tanner L-Edit Verilog VHDL

Area of Expertise

Academic: Research Circuits: Filters Circuits: Microcontrollers Circuits: Signal Processing Digital: RTL Digital: Synthesis Miscellaneous: Cryptography Miscellaneous: Neural Networks System: FPGA Programming SoC
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Hemaprasad Kothainambi

Design Verification Engineer with a keen sense of interest in Computer Architecture and RTL Design

Skills

Cadence Virtuoso System Verilog UVM SVA

Area of Expertise

Digital: Verification
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Franklin Guo

Skills

C/C++

Area of Expertise

Academic: Student Circuits: Microcontrollers
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Sameer Srivastava

cse undergrad

Skills

C/C++ Python Verilog

Area of Expertise

Academic: Student
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Angel Ramses Navarro Lopez

Skills

C/C++ Python System Verilog Verilog

Area of Expertise

Academic: Research Academic: Student Circuits: Microcontrollers Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification System: Test Equipment System: Test Programming