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"profiles" search for "interests": CPU

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Number of Results: 16

Bhawandeep Singh

Linkedin - https://www.linkedin.com/in/bhawandeep-singh-1b164517/ PhD student in CSE department in UCSC, advised by Prof. Jose Renau. My areas of majors are CPU design, digital design and embedded software.

Skills

C/C++ Python System Verilog Tcl/Tk Verilog

Area of Expertise

Academic: Research Academic: Student Academic: Teaching Circuits: Microcontrollers Digital: RTL System: FPGA Programming

gb6612

Skills

C/C++ Cadence Virtuoso Leadership ngspice Perl System Verilog Verilog

Area of Expertise

Business: Management Digital: RTL Digital: Synthesis Digital: Verification SoC: Floorplanning SoC: Verification System: Chip Editing System: FPGA Programming System: Quality Assurance

Day Make

Master course student from JP

Skills

C/C++ Verilog VHDL

Area of Expertise

Academic: Student

Dubravko Gacina

Embedded systems design engineer

Skills

C/C++ Python Software Developer

Area of Expertise

Circuits: Microcontrollers System: PCB

Daniel Pacheco

I like to work with Lua and C as well Power ISA is my go to architecture.

Skills

C/C++ System-C

Area of Expertise

Analog: Design System: Fabrication Process

Ufuk Yıldırım

Skills

C/C++ Verilog VHDL

Area of Expertise

Digital: DFT

Mumuji

Skills

C/C++

Area of Expertise

Academic: Student

Anthony Kung

Hi, I'm an Electrical & Computer Engineering + Computer Science student at Oregon State University.

Skills

C/C++ Python Software Developer System Verilog Verilog VHDL

Area of Expertise

Academic: Student Digital: RTL System: FPGA Programming

Zachary Berkowitz

Skills

C/C++ Python Verilog KiCAD

Area of Expertise

Academic: Student

Masahiro Suzuki

Skills

C/C++ System Verilog Tcl/Tk Verilog

Area of Expertise

Digital: Placement and Routing SoC: Floorplanning

Yuri Panchul

RTL design engineer with experience developing mobile GPUs (Samsung), high-end networking ASICs (Juniper) and CPU cores (MIPS). Co-author of lab manuals and online courses on FPGA design, RTL2GDSII flow and computer architecture. Founder of Verilog Meetup, a Silicon Valley and online community that develops open-source SystemVerilog examples targeting three niches: beginners, students who want to prepare for microarchitectural job interviews and university professors who want to avoid FPGA vendor lock (our examples are interoperable between Xilinx, Altera, Gowin and Lattice and compatible with ASIC flows, such as TinyTapeout and eFabless (in progress)).

Skills

C/C++ Perl System Verilog System-C Tcl/Tk Verilog VHDL

Area of Expertise

CAD: Tool Development Digital: RTL Digital: Verification System: FPGA Programming

Syed Manzoor Qasim

Skills

Leadership Magic CAD Matlab System Verilog Tanner L-Edit Verilog VHDL

Area of Expertise

Academic: Research Circuits: Filters Circuits: Microcontrollers Circuits: Signal Processing Digital: RTL Digital: Synthesis Miscellaneous: Cryptography Miscellaneous: Neural Networks System: FPGA Programming SoC

Hemaprasad Kothainambi

Design Verification Engineer with a keen sense of interest in Computer Architecture and RTL Design

Skills

Cadence Virtuoso System Verilog UVM SVA

Area of Expertise

Digital: Verification

Franklin Guo

Skills

C/C++

Area of Expertise

Academic: Student Circuits: Microcontrollers

Sameer Srivastava

cse undergrad

Skills

C/C++ Python Verilog

Area of Expertise

Academic: Student

Angel Ramses Navarro Lopez

Skills

C/C++ Python System Verilog Verilog

Area of Expertise

Academic: Research Academic: Student Circuits: Microcontrollers Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification System: Test Equipment System: Test Programming