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"profiles" search for "interests": asic design
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Number of Results: 21

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CHIRAG KASLIWAL

Specialized Engineer in VLSI Design

Skills

Analog/Digital Circuit Design C/C++ Scilab Verilog VLSI/ASIC and SoC Development

Area of Expertise

ASIC Design/Verification Digital-RTL
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Chandana Archita Bachhu

Skills

Circuit Design Perl Verilog VLSI/ASIC and SoC Development

Area of Expertise

ASIC Design/Verification Digital-RTL
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Semiu A. Olowogemo

Skills

C/C++ Cadence Virtuoso Perl Python Verilog VHDL

Area of Expertise

Academic: Research Digital: Placement and Routing Digital: RTL Digital: Synthesis Digital: Verification
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wisen wang

Skills

C/C++ Matlab Perl Python Software Developer Tcl/Tk Verilog VHDL

Area of Expertise

Academic: Research
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Gavisiddesh Javali

Motivated master' Student with progressive experience in ASIC Design and a real passion for it. An energetic - self-starter and team builder. Navigates high-stress situations and achieves goals on time and under budget. Always believing in learning and solving the problem through Technology.

Skills

Cadence Virtuoso Spectre Verilog VHDL

Area of Expertise

Academic: Student
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Safi Majid

Skills

Matlab Verilog

Area of Expertise

Academic: Research Digital: RTL System: PCB
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Colby Gilbert

Skills

Matlab Python Verilog

Area of Expertise

Academic: Student
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Dilip Singh

A researcher and VLSI guy

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Matlab Python System Verilog Tanner L-Edit Tcl/Tk Verilog

Area of Expertise

Academic: Research Circuits: Filters Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis System: FPGA Programming
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Sergio S

Skills

Cadence Virtuoso ngspice

Area of Expertise

Analog: Design Analog: Simulation CAD: Tool Development Circuits: Filters
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Krishna Sai Kanthan

Skills

C/C++ Cadence Virtuoso Perl System Verilog Tcl/Tk Verilog vim

Area of Expertise

Digital: Placement and Routing SoC: ESD System: Power Integrity
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Sajjad Ahmed

I am an graduate student of computer system engineering at Usman Institute of Technology. and working on RISCV based SoC designs since 2019 in Microelectronics Research Lab.

Skills

C C++ genus synthesis innovus digital implementation Matlab System Verilog

Area of Expertise

Academic: Research
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Muhammad Junaid

Skills

C/C++ Cadence Virtuoso Verilog

Area of Expertise

Academic: Student
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Pranav Vajreshwari

Working on ASIC, FPGA design flows. Interested in VLSI Design.

Skills

C/C++ Matlab Python Verilog

Area of Expertise

Academic: Research Academic: Student System: FPGA Programming
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Ashesh Pangma

I am a MSc. Electronic engineering graduate interested in VLSI design.

Skills

Verilog RTL

Area of Expertise

Analog: Design Analog: Layout Digital: RTL
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Nithin Angadi

Skills

C/C++ Cadence Virtuoso Matlab Python System Verilog Verilog

Area of Expertise

Academic: Student
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Nithin Angadi

I have an enthusiastic to design a SoC.

Skills

C/C++ Cadence Encounter Cadence Virtuoso

Area of Expertise

Academic: Student
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Nelson Rodriguez

An enthusiast of the Open Source World.

Skills

C/C++ Matlab Python Verilog Linux

Area of Expertise

Academic: Student
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Sriharsha Ganti

Dynamic and career-oriented VLSI Verification Trainee. Looking for a responsible position as a VLSI verification engineer with a view to utilize and enhance my skills and experience towards professional and personal growth.

Skills

C/C++ System Verilog Verilog perl sva c questa sim

Area of Expertise

Academic: Student
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Volkan Karaca

Digital Design Engineer

Skills

Matlab Verilog VHDL

Area of Expertise

Analog: Design Business: Management Circuits: Microcontrollers Circuits: Sensors System: FPGA Programming System: Signal Integrity
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Deepak B

I'm an ASIC Design Engineer with a focus on SoC verification. With over three years of experience in the field, I have had the privilege of successfully completing and taping out three projects. My expertise lies in ensuring the functionality and performance of complex System-on-Chip designs through thorough verification methodologies. Throughout my career, I have gained a deep understanding of the entire design flow, from specification and architectural exploration to RTL coding and verification. I am proficient in industry-standard verification languages and methodologies, such as SystemVerilog and UVM.

Skills

C/C++ Cadence Virtuoso Matlab uvm

Area of Expertise

digital Digital: Verification SoC: Verification
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Hao-Yen Tang

Hao-Yen Tang received his PhD degree from UC Berkeley Advised by Prof. Bernhard E. Boser, his PhD research, PMUT ultrasonic fingerprint sensor, convince InvenSense senior management to make a heavy investment to take this technology to mass market. At InvenSense he’s leading a multi-disciplinary system team for the next generation ultrasonic fingerprint sensor bringup, characterization and calibration, coordinating the works from different field including acoustic, MEMS, CMOS, FW, and SW. Currently, he serves as CTO/Co-Founder in the startup company UltraSense Systems. The company is aiming to transform any surface material into a Touch/Press user interface with it’s proprietary PiezoMEMS-CMOS technology. Dr. Tang is the recipient of 2016 ISSCC Best Paper Award (Lewis Winner Award for Outstanding Paper), 2015 SSCS Pre-Doctoral Award and 2015 ADI Outstanding Student Designer Award. Currently he holds 20+ granted patents, 20+ publications, and 2000+ citations.

Skills

C/C++ Cadence Virtuoso Leadership Python Spectre System Verilog Verilog

Area of Expertise

Academic: Research Academic: Teaching Analog: Simulation Analog: Verification Business: Management Business: Marketing Business: Patents Business: Sales Circuits: Filters Circuits: Power Management Circuits: Sensors Digital: RTL System: FPGA Programming System: PCB System: Test Programming