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"profiles" search for "interests": RTL

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Number of Results: 37

Buğra Tufan

Skills

C/C++ Matlab Python Tcl/Tk Verilog VHDL

Area of Expertise

Digital: RTL Digital: Synthesis Digital: Verification

bahadir turkoglu

Skills

C/C++ Matlab Verilog VHDL

Area of Expertise

Digital: RTL Digital: Synthesis System: FPGA Programming

Nicholas R. Smith

Cybersecurity nut, hardware hobbyist, nature enthusiast, amateur trumpet player. I also play World of Warcraft with my dad on the weekends.

Skills

C/C++ Matlab Python VHDL

Area of Expertise

Academic: Student

Ahsan Ali

Passionate Electrical Engineer with interest in computer architecture and SoCs.

Skills

C/C++ Matlab Python System Verilog Verilog

Area of Expertise

Academic: Student Circuits: Microcontrollers Digital: RTL Digital: Synthesis Digital: Verification

Jorge Scandaliaris

Teacher/researcher at the Electronics Department (DEEC) of Universidad Nacional de Tucumán, Argentina

Skills

C/C++ Electric CAD Magic CAD Python Verilog VHDL

Area of Expertise

Academic: Teaching Digital: RTL

MD AKRAMUDDIN

Skills

C/C++ Matlab Perl Verilog VLSI/ASIC and SoC Development

Area of Expertise

Digital-RTL

Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,

Skills

Cadence Encounter Cadence Virtuoso Calibre ngspice Python Tcl/Tk Verilog

Area of Expertise

Analog: Design Digital: Placement and Routing Digital: RTL Digital: Synthesis System: FPGA Programming

Mohammed Essam Abd El Samee Soliman

I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.

Skills

Leadership Matlab Perl Tcl/Tk Verilog VHDL

Area of Expertise

Digital: Placement and Routing Digital: RTL Digital: Synthesis

Dilip Singh

A researcher and VLSI guy

Skills

C/C++ Cadence Encounter Cadence Virtuoso Calibre Matlab Python System Verilog Tanner L-Edit Tcl/Tk Verilog

Area of Expertise

Academic: Research Circuits: Filters Circuits: Signal Processing Digital: Placement and Routing Digital: RTL Digital: Synthesis System: FPGA Programming

Aastha Dave

Undergraduate in ECE & Economics at BITS Pilani, India. An enthusiast in IC Design, VLSI and Physical Design.

Skills

C/C++ Eagle CAD Magic CAD Matlab ngspice Python Verilog

Area of Expertise

Academic: Research Academic: Student Analog: Design Analog: Simulation Circuits: Microcontrollers Circuits: Sensors

Bharathi M

working as Assistant Professor in Sree Vidyanikethan engineering college, Tirupati.

Skills

Eldo Verilog VHDL

Area of Expertise

Academic: Teaching Circuits: Signal Processing Digital: RTL Digital: Synthesis Digital: Verification System: Fabrication Process System: FPGA Programming

Shruti Prakash Gupta

I am a Senior Undergraduate in Electrical Engineering Department at IIT Gandhinagar, India. VLSI Design and the ability to tweak at the hardware level interest me a lot!

Skills

C/C++ Cadence Virtuoso Matlab Python System Verilog Verilog

Area of Expertise

Academic: Student CAD: Scripting Circuits: Microcontrollers Digital: RTL Digital: Verification SoC: Verification System: FPGA Programming

Pradeep Purushothaman Vadakkodathu

Skills

C/C++ Matlab System Verilog Tanner L-Edit Tcl/Tk Verilog

Area of Expertise

Digital: RTL Digital: Verification SoC: Verification System: FPGA Programming

Md Adil Raza

Skills

C/C++ Matlab Python Scilab Verilog

Area of Expertise

Academic: Student

RECEP GÜNAY

Received B.S. degree from Electrical and Electronics Engineering in Middle East Technical University, Turkey, in 2019. Currently, pursuing M.S. degree from Electronics Engineering in Bogazici University, Turkey. Research interests are computer architecture, hardware security and secure memory architecture

Skills

C/C++ Cadence Virtuoso Magic CAD System Verilog Verilog

Area of Expertise

Academic: Student Circuits: Memory Circuits: Microcontrollers Digital: RTL Digital: Synthesis Digital: Verification Miscellaneous: Cryptography System: FPGA Programming

Gurkirat Singh

Semiconductor professional with 12+ year experience in ASIC hardware design and methodology development. Main expertise is in chip STA signoff - top level, IO timing, High speed design timing, and good knowledge of RTL design, Physical design (Layout, CTS, Route, DRCs), Synthesis and Formal Verification. Have also completed business management studies and looking for interesting opportunities in chip product development and management.

Skills

Perl Tcl/Tk Verilog

Area of Expertise

Digital: RTL Digital: Synthesis sta

Faizan Khan

Skills

Cadence Virtuoso Calibre Matlab SPICE Opus Verilog

Area of Expertise

Analog: Design Analog: Layout Digital: RTL Digital: Synthesis

Ali Sabir

I have done electronic engineering from University of Engineering and Technology Peshawar in 2021, currently, i am doing MS in Electrical Engineering (Specialization in IC Design) from National University of Computer and Emerging Science(FAST-NUCES).

Skills

Cadence Genus Cadence Innovus Cadence Virtuoso Verilog

Area of Expertise

Analog: Layout Digital Synthesis Digital: Placement and Routing Digital: RTL

Aditya Mudgal

Doing Mtech in VLSI Design from IIIT Bangalore

Skills

C/C++ Cadence Virtuoso System Verilog Verilog

Area of Expertise

Academic: Student

Artur Darbinyan

Skills

Cadence Encounter Cadence Virtuoso Calibre Hercules Leadership SPICE Opus Verilog

Area of Expertise

Analog: Layout Business: Management Circuits: Memory Digital: Placement and Routing Digital: Synthesis SoC: Floorplanning

Geethanand N

Ex intel professional with over 5 years of experience in front end Vlsi

Skills

Perl System Verilog Tcl/Tk Verilog

Area of Expertise

CAD: Scripting Digital: RTL Digital: Verification SoC: Verification

Shubham Tonde

I am recently completed my post-graduation in VLSI and Embedded system from coep pune(India). I like to work in a backend design of VLSI.

Skills

Digital design pel sta Verilog

Area of Expertise

Digital: Placement and Routing Digital: RTL

Pruthvi raj Venkatesha

Skills

C/C++ Cadence Virtuoso System Verilog Verilog

Area of Expertise

Academic: Student

Pradeep C

I hold a Doctoral Degree in ‘Information and Communication Engineering,’ with 22+ years of experience in engineering education in various capacities. I have more than 30 research articles, presented and published in various National, International Journals and Conferences. My research interests are in the following domains and are not confined to VLSI, AIoT, Intelligent Transportation for Smart Cities in India, FPGA-based System Design, etc. My professional membership includes a Fellow, in the Institution of Engineers (India), a Fellow in the Institute of Electronics and Telecommunication Engineers, a Senior Member of IEEE, and a member of ISTE & ACM.

Skills

Leadership Verilog

Area of Expertise

Academic: Research Academic: Teaching Digital: RTL

Pradeep Kumar Velidi

I am a young student, growing high with a passion for VLSI. I am highly interested in working on high-speed low-power RTL chip design.

Skills

Cadence Virtuoso Matlab Python System Verilog Verilog vivado c RTL Design

Area of Expertise

Academic: Student

Dhruva Hegde

Masters Student (Integrated Circuits and Systems) at IIT Bombay.

Skills

Python Verilog VHDL

Area of Expertise

Academic: Research Circuits: Signal Processing Digital: RTL Digital: Synthesis

Mohamed Hossam

My name is Mohamed, I'm from Egypt, I'm studying at the electronics and communications engineering department at Cairo University, I'm an undergraduate student and my expected graduation year is 2024. I am interested in digital design track, I have done many projects related to this field. I am very passionate to get this experience and I am sure that I will do great work with you.

Skills

Tcl/Tk Verilog STA Power aware Design PnR DFT CDC Synopsys Design Compilier

Area of Expertise

Academic: Student

devang gajjar

Skills

C/C++ Perl Python System Verilog Verilog VHDL

Area of Expertise

Circuits: Microcontrollers Digital: RTL Digital: Synthesis Digital: Verification System: FPGA Programming

harvin iriawan

Skills

C/C++ Verilog

Area of Expertise

Digital: RTL

Usama ishfaq

Hello, my name is Usama Ishfaq. I am an electronics engineer with expertise in IC design. With years of experience in the industry, I have developed a strong understanding of the complexities involved in designing and developing integrated circuits. My passion for electronics and technology has driven me to constantly learn and innovate, ensuring that I stay up-to-date with the latest advancements in the field. I take pride in my ability to work collaboratively with teams and clients to deliver high-quality solutions that meet their specific needs. Thank you for taking the time to read my introduction.

Skills

C/C++ Cadence Virtuoso Matlab Verilog inovvus vivado

Area of Expertise

Analog: Design Analog: Layout Analog: Simulation Digital: RTL Digital: Synthesis Digital: Verification

Harsh Rajeshbhai Vagadiya

VLSI Enthusiastic

Skills

Verilog RTL Design

Area of Expertise

Academic: Student

Raj Nirmal

Skills

System Verilog Verilog computer Architecture RTL Design

Area of Expertise

Academic: Student

karunakar reddy kesamreddy

I am a professional in the field of Chip Design, Primary working on Synthesis, Physical Design, Static Timing Analysis and Physical Verification

Skills

Cadence Virtuoso Cadence Innovus Cadence Genus Synopsys Prime Time Synopsys IC Compiler 2 Synopsys Fusion Compiler Synopsys Design Compiler Tweaker Synopsys IC Validator Seimens Calibre