I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.
Computer Science Engineer with extensive hardware knowledge.
Analog full custom design experience of Low power VOltage regulators, Bandgap reference, calibration circuits and common mode receiver. worked on SERDES IP (up to 12Gbps) compliant with USB 3.1 and SATA protocols. AS ESD ENgineer for SERDES IP Improved existing ESD network simulation strategy and ESD network for robust ESD performance reliability and automated existing current density flow for ESD for better efficiency. Technology Nodes: 14nm(FINFet), 28nm(FDSOI) 28 nm,40nm,90nm,180nm (Bulk)
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
Mad Scientist
I'm a double-degree PhD candidate at University of São Paulo and Communauté Université Grenoble-Alpes with experience in analog/RF design and layouting at integrated technologies and interposers, with experience in slow-wave devices.
Analog VLSI Design Enthusiast
Electronic Engineer from the Federal University of Santa Catarina (Brazil). Master in Electrical Engineering from UFSC (thesis title: CMOS Ultra-Low-Voltage Ring Oscillators). Interested in the areas of Sensors, Ultra-Low Power Circuits and MOS modeling.
Student of Engineering in automation. Graduate in science of Engineering.
Assistant Professor at the Mechanical and Aerospace Engineering Department. The Henry Samueli School of Engineering. University of California, Irvine.
Professor of physics at the University of Texas at Arlington
I am Dr. Naushad Alam working as an Associate Professor in the Department of Electronics Engineering, Z H College of Engineering & Technology, Aligarh Muslim University, Aligarh, India. I received B. Tech. degree in Electronics & Communication Engineering from Jamia Millia Islamia, New Delhi in 2003, and M. Tech. Degree in Electronic Circuits & Systems Design from Aligarh Muslim University, Aligarh in 2009. I earned Ph.D. degree in Microelectronics from Indian Institute of Technology Roorkee, India in 2013. My doctoral work was on nanoscale circuit design considering the impact of process-induced mechanical stress. He has published 29 papers in SCI indexed journals that include 10 IEEE Transactions and 33 papers in reputed conferences. I have supervised two PhD thesis in the area of device-circuit co-design and presently supervising two more PhD students. I have also successfully executed a UGC funded research project on TFET based SRAM cell design for IoT Applications. My research interests include device-circuit co-design, robust nanoscale circuit design, low power circuit design, PVT tolerant circuit design, Near-Threshold/Sub-Threshold circuit design etc.
I am designed mixed signal ICs for Music, Audio, IoT and sensor applications.
IC designer with more than 25 years post Ph.D. experience. Specialising in RF, RFIC, analog and mixed-signal. Wide experience in Architecture, system and circuit design. RF front-end module design for cellular with CMOS PA. Over 40 patents issued.
Full time: Electronics Engineer with an interest in embedded systems solutions. I can take a project goal and design, develop, prototype, program, validate an embedded system reaching that goal. Part-time: Maker, interested in rapid prototyping, my lab has basic machines: CO2 Laser cutter, 3d printers, small milling machine. I've built 3 of my own 3d printers.
Designer specialized on VLSI radiation tolerant architectures and circuits
Starting small and hopefully moving towards big ideas. Interest in FPGAs, HDLs and Open Source Software and Hardware. Several decades of IT business experience.
I am a current Master's student in IC (Integrated Circuit) and Systems Design, as well as a Research Assistant at the Micro Nanoelectronics (MiNE) Lab located at SEECS NUST. I completed my Bachelor's degree in Electronics Engineering from UET Peshawar. As a member of the MiNE Lab team, I am involved in cutting-edge research in the field of micro and nanoelectronics, with a specific focus on the design and development of integrated circuits and systems. My academic and research background has provided me with a strong foundation in electronics engineering, and I am passionate about utilizing my skills to contribute to the development of innovative technologies in this field.
Estudiante de la Universidad nacional de Cordoba de la carrera de ingenieria Electronica investigador en sistemas embebido y programacion y microelectronica
Leader of a quantum hardware engineering team. Quantum hardware engineer, IBM quantum administrator/ developer, carpenter from the countryside in northern Arizona.
A PhD student working in WEST (Wireless Environmental Sensor Technology) Lab with a focus on Analog IC design.
B. Tech from IIT Bombay 73 elec and Masters from Philips Holland 75 and working on design and development 1975 till date
My research interests include systematic circuit synthesis techniques, modeling and simulation of linear and nonlinear circuits and systems, design and applications of fractional order chaotic oscillators, multi-objective optimization, evolutionary algorithms, and analog and mixed-signal design automation tools.
