Longtime innovator in analog and mixed signal design. US Patents US2773120A and US2560234A.
4+ years of VLSI Backend experience. Working as Physical Design Engineer. Expertise in Analog layouts, physical verification and Physical Design. Open to learn and explore other domains of VLSI design.
Graduated with a Micro-electronics Master from Bordeaux university, France, I have now 18 years of experience. Worked in France, England, Belgium and Brazil, within 5 companies. Implemented physical design flows, recruited, trained and supervised trainees to experienced engineers, I have a vast experience in setting up complete flow (2 companies were startups), as well as signing off important design within NXP and CSR, all to successful first time right silicons. Able to work in total independence as well as within a team, I consider myself as optimist, result focused, with attention to detail while keeping a good trade between time to market and risk taking.
Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.
A recent graduate student from Syracuse University major in Electrical Engineering with focus in VLSI Designs
I am a PhD student at Universiti Kebagsaan Malaysia. My research interests include application-specific hardware design, mainly to accelerate machine learning applications.
myself Mohd Parvez Khan, I am pursuing btech from dtu in ECE.I have keen interest in VLSI and Digital domain.
Actively Looking to work in a Semiconductor Organisation.I'm undergoing Masters in VLSI. I am Passionate about VLSI and semiconductors.He recently completed the 6-months training in Back-end VLSI at Entuple Technologies. And in addition to that specifically trained in STA, Synthesis and Physical Design by employing Cadence Tools. He is interested in and currently working on Open-Source tools related to VLSI (Openlane)
Fresher interested in asic physical design and looking for job opportunities in physical design engineering
Semiconductor professional with 12+ year experience in ASIC hardware design and methodology development. Main expertise is in chip STA signoff - top level, IO timing, High speed design timing, and good knowledge of RTL design, Physical design (Layout, CTS, Route, DRCs), Synthesis and Formal Verification. Have also completed business management studies and looking for interesting opportunities in chip product development and management.
Hi, I'm a student at UACJ and I like integrated circuit designs.
Professor, Department of Electrical and Computer Engineering Research Interests: Non-volatile Memories, solid state imaging systems, low power microelectronics, microelectronic process technology
My name is Mohamed, I'm from Egypt, I'm studying at the electronics and communications engineering department at Cairo University, I'm an undergraduate student and my expected graduation year is 2024. I am interested in digital design track, I have done many projects related to this field. I am very passionate to get this experience and I am sure that I will do great work with you.
VLSI DOMAIN SKILLS --------------------------- • Digital Electronics • HDL: Verilog • HVL: System Verilog • TB Methodology: UVM • Protocols: APB, UART, I2C, SPI • EDA Tools: Modelsim, Quartus Prime, Questasim. VLSI RTL SKILLS ---------------------- • Digital Skills : Combinational and Sequential circuits • FSM • Memories • Verilog : Data types • Operators • BA and NBA • Delays in Verilog • Begin-end and fork-join Blocks • System tasks and Function • Compiler directive • FSM Coding. VLSI VERIFICATION SKILLS ------------------------------------ • System Verilog HVL: Data Types • Memories • Interface • OOPS • Constraint Randomization • Threads • Functional coverage • CRCDV • SV Testbench (Hands on SV Testbench) • Universal Verification Methodology: UVM Objects and Components • UVM Factory • UVM Phases • UVM Configuration • TLM • Virtual Sequence and Sequencer • UVM Testbench (Hands on UVM Testbench).
I am a professional in the field of Chip Design, Primary working on Synthesis, Physical Design, Static Timing Analysis and Physical Verification
Senior security researcher, compiler/binary hacker, NFC ninja, hardware hacker with a FPGA hammer. Previously Pay Security.
Web Developer, Business Start up.
Cornell Tech ECE Master of Engineering Grad '24. Interested in startups and easier access to chip design and manufacturing!
