CEO of PineS Corp., Established in 1999, ASIC Design Service & Full Custom Layout Service.
I am a software developer, trying to learn about hardware design
Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,
I'm an experienced analog mixed signal layout design engineer. Have experience integrating IPs, Full chip layout design. I have hands on experience in TSMC 40LP, 28nm, 16ff, 7nm, GF 130nm process nodes.
VLSI Professional with 2.3 years of experience and adequate knowledge in RTL Design, UPF, SDC, Lint, CDC, Synthesis, Physical Design, STA and Scripting. I love Computers and I am interested in RISC V
I am a PhD. Telecommunication Engineer with 25 years of working experience in the industry. I started my career in 1997 as an IC Design Engineer, then I moved to other technical and management roles in the semiconductor and aerospace industries. Since 2017 I am also teaching IC Design at University for MsC. graduate students.
electronic engineer with knowledge in AMS design
Graduate equipped with a Bachelor of Engineering in Electronics and communication with a concentration in Semiconductor and VLSI design with hands-on experience in CAD tools and to join a reputable organization to begin a fulfilling, lifelong career.
I'm an ASIC Design Engineer with a focus on SoC verification. With over three years of experience in the field, I have had the privilege of successfully completing and taping out three projects. My expertise lies in ensuring the functionality and performance of complex System-on-Chip designs through thorough verification methodologies. Throughout my career, I have gained a deep understanding of the entire design flow, from specification and architectural exploration to RTL coding and verification. I am proficient in industry-standard verification languages and methodologies, such as SystemVerilog and UVM.
I am software engineer of 20+ years experience in board bring up of multiple SoCs in Linux / QNX/RTOS/Baremetal. Mostly done projects on automotive and industrial automation domains
As a PhD candidate in Electrical and Computer Engineering at Rowan University, I am passionate about designing domain-specific customized hardware accelerators using Hardware Description Languages. I am currently a Graduate Research and Teaching Fellow, working on projects related to computer hardware architecture, digital design, and VLSI design. I have expertise in VHDL, VERILOG, and Scala, and experience with testing, debugging, simulating, and waveform analysis tools. I also have a strong background in computer architecture, SOC design, and reversible computing, and knowledge of C/C++ programming languages. Additionally, I have secured multiple grants from the National Science Foundation for conducting customer discovery interviews in the domain of scientific computing. I have also published several papers in international journals and received the Young Researcher Award in 2020. I am a team player, a leader, a mentor, and a public speaker, with skills in interviewing, collaborating, and empowering others.
Greetings! I, Devang Sharma am a B.Tech final year student studying at Jaypee Institute, Noida. I am a VLSI-enthusiast and posses moderate to advanced-level skillset(at B.Tech level). I have studied about ASIC Design Flow and learnt several HDLs(Verilog, SV, UVM).
