I am a experienced analog and mixed-signal circuits designer, using standard and/or custom circuits ( external IPs or from my own design ).
VLSI circuit design engineer with significant experience in microprocessor design in semiconductor processes from 65nm to 10nm. Provided register file designs and design training for Intel Big Core and SOC projects. Helped create semi-automated array layout methodology. Established cross-organizational methodology for variation analysis in register files. Converged memory IP handling across multiple organizations.
I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.
Physical Design Engineer, 5 Years of experience and always fascinate about learning new concepts. Open to understand & take participate in Open Source.
I'm VLSI Design Engineer aspirant and like to work on design challenges in VLSI domain. I like to keep updated of cutting-edge technology in my field of interest.
I'm hardworking, I'm smart at doing things, I'm analytical, and passionate to my work. I love to do programming.
Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.
Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design. Fiction writer (National Literature Award for Novel, 2011, Costa Rica)
Electrical engineer with PhD in micro-electronics, and more than 23 years experience in the automotive industry. Specialized in the development of CAD tools to support mixed-signal and smart-power IC design. Founder of SYDELITY b.v. a start-up company offering services and products accellerating system-level simulations.
I am an electronics engineer from Montenegro, specializing in integrated electronics design and simulation. My greatest interest is in the field of analog ICs, especially applications in the medical field. Other interests are mathematics(dynamical systems foremost), physics simulations using numerical methods and so on. I also like to spend my spare time making a game engine in C++
PhD student working on a superconducting FPGA design aiming to work on neuromorphic computing in the future.
I'm a double-degree PhD candidate at University of São Paulo and Communauté Université Grenoble-Alpes with experience in analog/RF design and layouting at integrated technologies and interposers, with experience in slow-wave devices.
A master's student studying the design of electronic devices
Graduate student passionate about integrated circuit design for biomedical applications
I am a professor in the department of electrical and computer engineering at University of Cincinnati. My areas of expertise are: CMOS, Beyond-CMOS devices such as RRAM, FeFETs, gated-RRAM, TFTs, novel device design, fabrication, and testing, neuromorphic computing, and hardware security.
I am Dr. Naushad Alam working as an Associate Professor in the Department of Electronics Engineering, Z H College of Engineering & Technology, Aligarh Muslim University, Aligarh, India. I received B. Tech. degree in Electronics & Communication Engineering from Jamia Millia Islamia, New Delhi in 2003, and M. Tech. Degree in Electronic Circuits & Systems Design from Aligarh Muslim University, Aligarh in 2009. I earned Ph.D. degree in Microelectronics from Indian Institute of Technology Roorkee, India in 2013. My doctoral work was on nanoscale circuit design considering the impact of process-induced mechanical stress. He has published 29 papers in SCI indexed journals that include 10 IEEE Transactions and 33 papers in reputed conferences. I have supervised two PhD thesis in the area of device-circuit co-design and presently supervising two more PhD students. I have also successfully executed a UGC funded research project on TFET based SRAM cell design for IoT Applications. My research interests include device-circuit co-design, robust nanoscale circuit design, low power circuit design, PVT tolerant circuit design, Near-Threshold/Sub-Threshold circuit design etc.
An enthusiast of the Open Source World.
Full time: Electronics Engineer with an interest in embedded systems solutions. I can take a project goal and design, develop, prototype, program, validate an embedded system reaching that goal. Part-time: Maker, interested in rapid prototyping, my lab has basic machines: CO2 Laser cutter, 3d printers, small milling machine. I've built 3 of my own 3d printers.
ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.
Engineer / VP
Research scientist working in a MOS technology support for teaching at academic institutions.
A software developer, technology manager, and hardware tinkerer aspiring to imbue slices of crystals with intelligence.
My name is Mohamed, I'm from Egypt, I'm studying at the electronics and communications engineering department at Cairo University, I'm an undergraduate student and my expected graduation year is 2024. I am interested in digital design track, I have done many projects related to this field. I am very passionate to get this experience and I am sure that I will do great work with you.
I have over thirty years of experience in the semiconductor industry, having worked in fab, EDA and design engineering. have built and led large, geographically distributed teams at a senior manager level. I am passionate about developing talent and skills, particularly in young people from socio-economically underprivileged backgrounds.
An aspiring young electrical engineering student from Pakistan trying to learn and build my expertise in the FPGA/SoC development world with Xilinx Zynq platforms. Working on a machine learning accelerator on Digilent Cora Z7 (Zynq 7000 series SoC) board for my senior year project.
B. Tech from IIT Bombay 73 elec and Masters from Philips Holland 75 and working on design and development 1975 till date
From Mining Gems in the field to mining data about gems and developing bleeding edge Gemological/Geological/Geophysical/Geochemical/Geospatial/Spectroscopic and other Survey, Testing, Measuring, Databasing, Retrieval, and Analytical Devices/Software/Tradecraft as well as beyond crystal unit level precision automated faceting/cutting/polishing/cabbing/carving/lapidary instruments and even 500 picometer diameter diamond polish... I do it all. Anyone in the industry wanting to spice up and drastically increase the efficiency and ROI on their wafer lapping/polishing capabilities: help me...help you...get ahead of the EUV/DUV/3nm and finer processes (my system has an RI value of less than 500pm... THAT is smaller than 8 carbon atoms in a cubic formation...carbon...not silicon...
I am a materials scientist specializing in micro and nanofabrication, semiconductor devices physics and semiconductor materials characterization. I would like to learn more about chip design.
My research interests include systematic circuit synthesis techniques, modeling and simulation of linear and nonlinear circuits and systems, design and applications of fractional order chaotic oscillators, multi-objective optimization, evolutionary algorithms, and analog and mixed-signal design automation tools.
I graduated with a computer engineering BS/MS from the University of Maryland College park. I now work in industry at a medical device company.
Senior security researcher, compiler/binary hacker, NFC ninja, hardware hacker with a FPGA hammer. Previously Pay Security.
